Inventor

ALEXANDER KHARY J

US69 patents

⚠️ This page may combine multiple inventors who share the name “ALEXANDER KHARY J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ALEXANDER KHARY J

IBM

Load queue entry reuse for operand store compare history table update

Accuracy of operand store compare prediction using confidence counter

Accuracy of operand store compare prediction using confidence counter

Load queue entry reuse for operand store compare history table update

Restricting processing within a processor to facilitate transaction completion

Store forwarding cache

Method and system for early instruction text based operand store compare reject avoidance

Resource mapping in multi-threaded central processor units

Load queue entry reuse for operand store compare history table update

Accuracy of operand store compare prediction using confidence counter

Controlling execution of threads in a multi-threaded processor

Sharing program interrupt logic in a multithreaded processor

Store forwarding cache

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

Authenticating features of virtual server system

End-to-end protection for shrouded virtual servers

Store forwarding cache

Store forwarding cache

Multilevel cache system

Store buffer for transactional memory

Method, system, and computer program product for selectively accelerating early instruction processing

Methods, systems, and computer program products for recovering from branch prediction latency

Delayed allocation of an out-of-order queue entry and based on determining that the entry is unavailable, enable deadlock avoidance involving reserving one or more entries in the queue, and disabling deadlock avoidance based on expiration of a predetermined amount of time

Method, system and computer program product for an implicit predicted return from a predicted subroutine

Accelerated execution of execute instruction target

Load and store ordering for a strongly ordered simultaneous multithreading core

Resource mapping in multi-threaded central processor units

Load and store ordering for a strongly ordered simultaneous multithreading core

Accelerated execution of execute instruction target

Sharing program interrupt logic in a multithreaded processor

Store forwarding cache

Controlling execution of threads in a multi-threaded processor

Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB)

Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB)

Accelerated execution of target of execute instruction

Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB)

ALEXANDER KHARY J

Early instruction text based operand store compare reject avoidance

System and method for Controlling restarting of instruction fetching using speculative address computations

Facilitating processing in a computing environment using an extended drain instruction

History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties

Cracking destructively overlapping operands in variable length instructions

Tracking transactional execution footprint

Monitoring a value in storage without repeated storage access

Mitigating conflicts for shared cache lines

Facilitating processing in a computing environment using an extended drain instruction

Determining the logical address of a transaction abort

Restricting processing within a processor to facilitate transaction completion

ALEXANDER GREGORY W

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

PRASKY BRIAN R

Hard error detection