Inventor
CURRAN BRIAN W
US27 patents
Patents
27 patentsUS5568075AOct 22, 1996
Timing signal generator
IBM69 citations95
US5572736ANov 5, 1996
Method and apparatus for reducing bus noise and power consumption
IBM32 citations92
US5278967AJan 11, 1994
System for providing gapless data transfer from page-mode dynamic random access memories
IBM39 citations92
US5032985AJul 16, 1991
Multiprocessor system with memory fetch buffer invoked during cross-interrogation
IBM45 citations88
US6816824B2Nov 9, 2004
Method for statically timing SOI devices and circuits
IBM13 citations84
US6661262B1Dec 9, 2003
Frequency doubling two-phase clock generation circuit
IBM14 citations84
US6426661B1Jul 30, 2002
Clock distribution with constant delay clock buffer circuit
IBM17 citations84
US5574921ANov 12, 1996
Method and apparatus for reducing bus noise and power consumption
IBM18 citations82
US5939915AAug 17, 1999
Noise-immune pass gate latch
IBM16 citations74
US5428762AJun 27, 1995
Expandable memory having plural memory cards for distributively storing system data
IBM16 citations74
US9619385B2Apr 11, 2017
Single thread cache miss rate estimation
IBM3 citations73
US5554946ASep 10, 1996
Timing signal generator
IBM14 citations73
US5479640ADec 26, 1995
Memory access system including a memory controller with memory redrive circuitry
IBM13 citations69
US11379228B2Jul 5, 2022
Microprocessor including an efficiency logic unit
IBM0 citations62
US6882205B2Apr 19, 2005
Low power overdriven pass gate latch
IBM3 citations62
US6768365B2Jul 27, 2004
Low power reduced voltage swing latch
IBM2 citations62
US6657471B1Dec 2, 2003
High performance, low power differential latch
IBM3 citations62
US6966046B2Nov 15, 2005
CMOS tapered gate and synthesis method
IBM3 citations59
US7676779B2Mar 9, 2010
Logic block timing estimation using conesize
IBM2 citations57
US10540183B2Jan 21, 2020
Accelerated execution of execute instruction target
IBM0 citations52
US9875107B2Jan 23, 2018
Accelerated execution of execute instruction target
IBM0 citations52
US9626293B2Apr 18, 2017
Single-thread cache miss rate estimation
IBM0 citations52
US9575529B2Feb 21, 2017
Voltage droop reduction in a processor
IBM1 citations52
US9389865B1Jul 12, 2016
Accelerated execution of target of execute instruction
IBM1 citations52
US10514911B2Dec 24, 2019
Structure for microprocessor including arithmetic logic units and an efficiency logic unit
IBM0 citations51
US10503503B2Dec 10, 2019
Generating design structure for microprocessor with arithmetic logic units and an efficiency logic unit
IBM0 citations51
US7243170B2Jul 10, 2007
Method and circuit for reading and writing an instruction buffer
IBM0 citations38