Inventor
HUTTON DAVID S
US28 patents
⚠️ This page may combine multiple inventors who share the name “HUTTON DAVID S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
21 patentsUS7577795B2Aug 18, 2009
Disowning cache entries on aging out of the entry
IBM17 citations92
US7266580B2Sep 4, 2007
Modular binary multiplier for signed and unsigned operands of variable widths
IBM10 citations83
US7475193B2Jan 6, 2009
Separate data and coherency cache directories in a shared cache in a multiprocessor system
IBM9 citations82
US7975130B2Jul 5, 2011
Method and system for early instruction text based operand store compare reject avoidance
IBM8 citations81
US7853635B2Dec 14, 2010
Modular binary multiplier for signed and unsigned operands of variable widths
IBM6 citations73
US7861064B2Dec 28, 2010
Method, system, and computer program product for selectively accelerating early instruction processing
IBM2 citations63
US10884754B2Jan 5, 2021
Infinite processor thread balancing
IBM0 citations61
US7949972B2May 24, 2011
Method, system and computer program product for exploiting orthogonal control vectors in timing driven synthesis
IBM2 citations57
US10540183B2Jan 21, 2020
Accelerated execution of execute instruction target
IBM0 citations52
US10365928B2Jul 30, 2019
Suppress unnecessary mapping for scratch register
IBM0 citations52
US9875107B2Jan 23, 2018
Accelerated execution of execute instruction target
IBM0 citations52
US9389865B1Jul 12, 2016
Accelerated execution of target of execute instruction
IBM1 citations52
US7971034B2Jun 28, 2011
Reduced overhead address mode change management in a pipelined, recycling microprocessor
IBM1 citations52
US7913067B2Mar 22, 2011
Method and system for overlapping execution of instructions through non-uniform execution pipelines in an in-order processor
IBM0 citations52
US9766896B2Sep 19, 2017
Optimizing grouping of instructions
IBM0 citations51
US9710278B2Jul 18, 2017
Optimizing grouping of instructions
IBM0 citations51
US7490121B2Feb 10, 2009
Modular binary multiplier for signed and unsigned operands of variable widths
IBM0 citations51
US10558464B2Feb 11, 2020
Infinite processor thread balancing
IBM0 citations50
US10599431B2Mar 24, 2020
Managing backend resources via frontend steering or stalls
IBM0 citations41
US7895538B2Feb 22, 2011
System and method for providing a common instruction table
IBM0 citations41
US7921279B2Apr 5, 2011
Operand and result forwarding between differently sized operands in a superscalar processor
IBM0 citations40
HUTTON DAVID S
3 patentsUS8131945B2Mar 6, 2012
Disowning cache entries on aging out of the entry
HUTTON DAVID S3 citations60
US8566529B2Oct 22, 2013
Method, system and computer program product for generalized LRU in cache and memory performance analysis and modeling
HUTTON DAVID S2 citations59
US8423968B2Apr 16, 2013
Template-based vertical microcode instruction trace generation
HUTTON DAVID S0 citations39