Inventor
GRZYMKOWSKI PAUL J
US11 patents
⚠️ This page may combine multiple inventors who share the name “GRZYMKOWSKI PAUL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
7 patentsUS9881694B2Jan 30, 2018
Built-in-self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
IBM6 citations82
US10971243B2Apr 6, 2021
Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
IBM1 citations71
US10692584B2Jun 23, 2020
Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
IBM1 citations71
US11295829B2Apr 5, 2022
Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
IBM0 citations61
US10553302B2Feb 4, 2020
Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
IBM0 citations51
US7904839B2Mar 8, 2011
System and method for controlling access to addressable integrated circuits
IBM0 citations40
US7831936B2Nov 9, 2010
Structure for a system for controlling access to addressable integrated circuits
IBM0 citations40
GLOBALFOUNDRIES INC
3 patentsUS9760673B2Sep 12, 2017
Application specific integrated circuit (ASIC) test screens and selection of such screens
GLOBALFOUNDRIES INC0 citations51
US10295592B2May 21, 2019
Pre-test power-optimized bin reassignment following selective voltage binning
GLOBALFOUNDRIES INC0 citations49
US9759767B2Sep 12, 2017
Pre-test power-optimized bin reassignment following selective voltage binning
GLOBALFOUNDRIES INC0 citations49