Inventor
ROVEDO NIVO
US42 patents
⚠️ This page may combine multiple inventors who share the name “ROVEDO NIVO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
38 patentsUS4671851AJun 9, 1987
Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique
IBM189 citations98
US4648937AMar 10, 1987
Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer
IBM348 citations98
US6429091B1Aug 6, 2002
Patterned buried insulator
IBM55 citations96
US6403482B1Jun 11, 2002
Self-aligned junction isolation
IBM58 citations96
US5654917AAug 5, 1997
Process for making and programming a flash memory array
IBM47 citations96
US5541130AJul 30, 1996
Process for making and programming a flash memory array
IBM39 citations96
US4868135ASep 19, 1989
Method for manufacturing a Bi-CMOS device
IBM77 citations96
US5622881AApr 22, 1997
Packing density for flash memories
IBM42 citations95
US6544874B2Apr 8, 2003
Method for forming junction on insulator (JOI) structure
IBM48 citations93
US5681770AOct 28, 1997
Process for making and programming a flash memory array
IBM22 citations93
US5650345AJul 22, 1997
Method of making self-aligned stacked gate EEPROM with improved coupling ratio
IBM27 citations93
US4641170AFeb 3, 1987
Self-aligned lateral bipolar transistors
IBM32 citations93
US5369049ANov 29, 1994
DRAM cell having raised source, drain and isolation
IBM45 citations92
US5334281AAug 2, 1994
Method of forming thin silicon mesas having uniform thickness
IBM22 citations92
US4729006AMar 1, 1988
Sidewall spacers for CMOS circuit stress relief/isolation and method for making
IBM51 citations92
US7279758B1Oct 9, 2007
N-channel MOSFETs comprising dual stressors, and methods for forming the same
IBM24 citations91
US5892257AApr 6, 1999
Packing density for flash memories
IBM30 citations91
US5643813AJul 1, 1997
Packing density for flash memories by using a pad oxide
IBM30 citations91
US5264395ANov 23, 1993
Thin SOI layer for fully depleted field effect transistors
IBM33 citations91
US6352903B1Mar 5, 2002
Junction isolation
IBM24 citations89
US6071767AJun 6, 2000
High performance/high density BICMOS process
IBM21 citations89
US7960798B2Jun 14, 2011
Structure and method to form multilayer embedded stressors
IBM11 citations84
US7785950B2Aug 31, 2010
Dual stress memory technique method and related structure
IBM9 citations84
US7618866B2Nov 17, 2009
Structure and method to form multilayer embedded stressors
IBM11 citations84
US7442619B2Oct 28, 2008
Method of forming substantially L-shaped silicide contact for a semiconductor device
IBM9 citations84
US6256755B1Jul 3, 2001
Apparatus and method for detecting defective NVRAM cells
IBM16 citations84
US6916729B2Jul 12, 2005
Salicide formation method
IBM16 citations83
US5672892ASep 30, 1997
Process for making and programming a flash memory array
IBM14 citations82
US4551906ANov 12, 1985
Method for making self-aligned lateral bipolar transistors
IBM21 citations82
US6525340B2Feb 25, 2003
Semiconductor device with junction isolation
IBM16 citations77
US6391703B1May 21, 2002
Buried strap for DRAM using junction isolation technique
IBM11 citations74
US4982257AJan 1, 1991
Vertical bipolar transistor with collector and base extensions
IBM16 citations70
US4957875ASep 18, 1990
Vertical bipolar transistor
IBM17 citations70
US8034692B2Oct 11, 2011
Structure and method for manufacturing asymmetric devices
IBM2 citations63
US8017483B2Sep 13, 2011
Method of creating asymmetric field-effect-transistors
IBM5 citations62
US7473608B2Jan 6, 2009
N-channel MOSFETs comprising dual stressors, and methods for forming the same
IBM4 citations61
US6797569B2Sep 28, 2004
Method for low topography semiconductor device formation
IBM0 citations49
US6624486B2Sep 23, 2003
Method for low topography semiconductor device formation
IBM1 citations49