Inventor
GAGLIARDO MICHAEL A
US10 patents
Patents
10 patentsUS5043874AAug 27, 1991
Memory configuration for use with means for interfacing a system control unit for a multi-processor system with the system main memory
DIGITAL EQUIPMENT CORP56 citations95
US5235693AAug 10, 1993
Method and apparatus for reducing buffer storage in a read-modify-write operation
DIGITAL EQUIPMENT CORP50 citations92
US5014273AMay 7, 1991
Bad data algorithm
DIGITAL EQUIPMENT CORP31 citations92
US5008886AApr 16, 1991
Read-modify-write operation
DIGITAL EQUIPMENT CORP37 citations92
US5408641AApr 18, 1995
Programmable data transfer timing
DIGITAL EQUIPMENT CORP6 citations72
US5371874ADec 6, 1994
Write-read/write-pass memory subsystem cycle
DIGITAL EQUIPMENT CORP13 citations72
US5185875AFeb 9, 1993
Method and apparatus for reducing memory read latency in a shared memory system with multiple processors
DIGITAL EQUIPMENT CORP18 citations72
US5335337AAug 2, 1994
Programmable data transfer timing
DIGITAL EQUIPMENT CORP5 citations61
US5313623AMay 17, 1994
Method and apparatus for performing diagnosis scanning of a memory unit regardless of the state of the system clock and without affecting the store data
DIGITAL EQUIPMENT CORP5 citations60
US5255381AOct 19, 1993
Mode switching for a memory system with diagnostic scan
DIGITAL EQUIPMENT CORP3 citations60