Inventor

PARAT KRISHNA K

US83 patents

⚠️ This page may combine multiple inventors who share the name “PARAT KRISHNA K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARAT KRISHNA K

MICRON TECHNOLOGY INC

Apparatuses and methods to control body potential in memory operations

Cell pillar structures and integrated flows

Floating gate memory cells in vertical memory

Apparatus and methods including source gates

Apparatuses and methods to control body potential in memory operations

Apparatus and methods including source gates

Apparatus and methods including source gates

Apparatuses and methods to control body potential in 3D non-volatile memory operations

Floating gate memory cells in vertical memory

Apparatuses and methods to control body potential in 3D non-volatile memory operations

Floating gate memory cells in vertical memory

Apparatus and methods including source gates

Cell pillar structures and integrated flows

Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells

Programming memories with multi-level pass signal

Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells

Multi-decks memory device including inter-deck switches

In-field block retiring

Apparatus and methods including source gates

Cell pillar structures and integrated flows

Memory cell pillar including source junction plug

Apparatuses and methods to control body potential in 3D non-volatile memory operations

Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells

Floating gate memory cells in vertical memory

Cell pillar structures and integrated flows

Programming memories with multi-level pass signal

INTEL CORP

Self-aligned contact process in semiconductor fabrication

Depletion and enhancement MOSFETs with electrically trimmable threshold voltages

Self-aligned contact process in semiconductor fabrication and device therefrom

Erase and soft program for vertical NAND flash

Method and apparatus for providing electrostatic discharge protection for high voltage inputs

Method and system for reducing program disturb degradation in flash memory

Dynamically compensating for degradation of a non-volatile memory device

Three dimensional memory structure

Multi-pulse programming for memory

Three dimensional memory structure

Program VT spread folding for NAND flash memory programming

Non-volatile memory with storage nodes having a radius of curvature

Erase and soft program for vertical NAND flash

Segmented erase in memory

TANG SANH D

Methods of forming circuitry components and methods of forming an array of memory cells

Contact integration for three-dimensional stacking semiconductor devices

SINHA NISHANT

Methods for forming three-dimensional memory devices, and related structures

GODA AKIRA

Apparatus and methods including source gates

GOLDMAN MATTHEW

Method and system to obtain state confidence data using multistrobe read of a non-volatile memory

LIU HAITAO

Vertical memory cell string with dielectric in a portion of the body

KALAVADE PRANAV

Automatic selective slow program convergence

DAMLE PRASHANT S

Memory device having improved programming operation

SIMSEK-EGE FATMA A

Tungsten salicide gate source for vertical NAND string to control on current and cell pillar fabrication

PARAT KRISHNA K

In-field block retiring