Inventor

LAI PO-SHEN

US25 patents

⚠️ This page may combine multiple inventors who share the name “LAI PO-SHEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAI PO-SHEN

ADVANCED MICRO DEVICES INC

Network interface device architecture for storing transmit and receive data in a random access buffer memory across independent clock domains

Apparatus and method in a network interface device for asynchronously generating SRAM full and empty flags using coded read and write pointer values

System for transferring frame data by transferring the descriptor index data to identify a specified amount of data to be transferred stored in the host computer

Apparatus and method in a network interface device for selectively supplying long bit information related to a data frame to a buffer memory and a read controller for initiation of data transfers

Apparatus and method in a network interface device for storing tracking information indicating stored data status between contending memory controllers

Apparatus and method in a network interface device for storing status information contiguous with a corresponding data frame in a buffer memory

Apparatus and method in a network interface device for storing a data frame and corresponding tracking information in a buffer memory

Network interface device for accessing data stored in buffer memory locations defined by programmable read pointer information

Apparatus and method in a network interface device for storing receiving frame status in a holding register

Apparatus and method for automatic sense and establishment of 5V and 3.3V operation

Apparatus and method in a network interface for recovering from complex PCI bus termination conditions

Apparatus and method for determining a presence of a stored data frame in a random access memory independent of read and write clock domains

Apparatus and method in a network interface device for determining data availability in a random access memory

SANDISK CORP

Multi-regulator power delivery system for ASIC cores

Self-configurable multi-regulator ASIC core power delivery

Exclusive-option chips and methods with all-options-active test mode

Integrated circuit and manufacturing process facilitating selective configuration for electromagnetic compatibility

Extending drive capability in integrated circuits utilizing programmable-voltage output circuits

SANDISK TECHNOLOGIES LLC

Efficient control of memory core circuits

Multicore on-die memory microcontroller

Efficient control of memory core circuits

(unassigned)

Architecture and method for flushing non-transmitted portions of a data frame from a transmitted FIFO buffer

LASSA PAUL A

Optionally bonding either two sides or more sides of integrated circuits

LASSA PAUL

Selectively powered data interfaces

LAI PO-SHEN

Exclusive-option chips and methods with all-options-active test mode