Inventor

LIM CHOOI PEI

MY19 patents

⚠️ This page may combine multiple inventors who share the name “LIM CHOOI PEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIM CHOOI PEI

ALTERA CORP

3D built-in self-test scheme for 3D assembly defect detection

Techniques for precision biasing output driver for a calibrated on-chip termination circuit

Clock signal networks for structured ASIC devices

Methods and apparatus for reducing power in clock distribution networks

Method and apparatus for providing signal routing control

Periphery clock signal distribution circuitry for structured ASIC devices

Multi-layer distributed network

Mask set for fabricating integrated circuits and method of fabricating integrated circuits

Clock signal networks for structured ASIC devices

INTEL CORP

Techniques for clock signal transmission in integrated circuits and interposers

Techniques for clock signal transmission in integrated circuits and interposers

Via configurable edge-combiner with duty cycle correction

Clock synchronization in multi-die field programmable gate array devices

LIM CHOOI PEI

Systems including an I/O stack and methods for fabricating such systems

Clock signal networks for structured ASIC devices

OH KEONG HONG

Multi-layer distributed network

Multi-layer distributed network

LOH SIANG POH

Stacked integrated circuit with redundancy in die-to-die interconnects

PLOFSKY JORDAN

Mask set for fabricating integrated circuits and method of fabricating integrated circuits