Inventor

TRIPSAS NICHOLAS H

US53 patents

⚠️ This page may combine multiple inventors who share the name “TRIPSAS NICHOLAS H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TRIPSAS NICHOLAS H

ADVANCED MICRO DEVICES INC

Use of high-K dielectric material in modified ONO structure for semiconductor devices

Use of high-k dielectric materials in modified ONO structure for semiconductor devices

Method of forming copper sulfide for memory cell

Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same

Polymer memory device formed in via opening

Method(s) facilitating formation of memory cell(s) and patterned conductive

Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer

Planar polymer memory device

Implant damage removal by laser thermal annealing

Self assembly of conducting polymer for formation of polymer memory cell

Laser thermal annealing method for high dielectric constant gate oxide films

Memory device and method of making

Memory device and method of making

Non-charging critical dimension SEM metrology standard

Stacked organic memory devices and methods of operating and fabricating

Stacked organic memory devices and methods of operating and fabricating

Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same

High density dual bit flash memory cell with non planar structure

Ion source and method for using same

Semiconductor device having a reduced height floating gate

Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration

Buried silicide local interconnect with sidewall spacers and method for making the same

Stacked organic memory devices and methods of operating and fabricating

Utilization of a Ta-containing cap over copper to facilitate concurrent formation of copper vias and memory element structures

Source bus formation for a flash memory using silicide

Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation

Methods and systems for recovering data in a nonvolatile memory array

Etch damage repair with thermal annealing

Non-volatile memory dielectric as charge pump dielectric

Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices

Dopant profile spreading for arsenic source/drain

Memory cell structure for elimination of oxynitride (ONO) etch residue and polysilicon stringers

Buried silicide local interconnect with sidewall spacers and method for making the same

Buried silicide local interconnect with sidewall spacers and method for making the same

Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same

Method for repairing damage to charge trapping dielectric layer from bit line implantation

Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation

Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation

Nitridation of gate oxide by laser processing

Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices

Approach for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects

SPANSION LLC

Diode array architecture for addressing nanoscale resistive memory arrays

Memory device with a selection element and a control line in a substantially similar layer

Memory device with a selection element and a control line in a substantially similar layer

Preamorphization to minimize void formation

Stacked organic memory devices and methods of operating and fabricating

Systems and methods for a memory and/or selection element formed within a recess in a metal line

Protection of active layers of memory cells during processing of other elements

Semiconductor device built on plastic substrate

Processing a copolymer to form a polymer memory cell