Inventor
NGUYEN KHA
VN48 patents
⚠️ This page may combine multiple inventors who share the name “NGUYEN KHA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MARVELL INT LTD
13 patentsUS7849259B1Dec 7, 2010
Disk controller response handler for write commands
MARVELL INT LTD23 citations89
US7836230B1Nov 16, 2010
Managing multiple host requests in queued commands that corresponds to receipt of stored acknowledgement commands from the host
MARVELL INT LTD13 citations83
US9021147B1Apr 28, 2015
Command queuing in disk drives
MARVELL INT LTD4 citations82
US7613887B1Nov 3, 2009
System and method for managing a memory storage device
MARVELL INT LTD7 citations73
US7484037B2Jan 27, 2009
Disk controller configured to perform out of order execution of write operations
MARVELL INT LTD7 citations72
US9547556B1Jan 17, 2017
Restart operation with logical blocks in queued commands
MARVELL INT LTD1 citations62
US8700966B1Apr 15, 2014
Restart operation with logical blocks in queued commands
MARVELL INT LTD1 citations62
US7953907B1May 31, 2011
Concurrent input/output control and integrated error management in FIFO
MARVELL INT LTD4 citations62
US7949838B1May 24, 2011
System and method for managing a memory storage device
MARVELL INT LTD3 citations62
US8032674B2Oct 4, 2011
System and method for controlling buffer memory overflow and underflow conditions in storage controllers
MARVELL INT LTD6 citations54
US8850136B1Sep 30, 2014
Method and apparatus for coordinating transmission of data between a storage medium and a host
MARVELL INT LTD0 citations51
US7984252B2Jul 19, 2011
Storage controllers with dynamic WWN storage modules and methods for managing data and connections between a host and a storage device
MARVELL INT LTD0 citations48
US7757009B2Jul 13, 2010
Storage controllers with dynamic WWN storage modules and methods for managing data and connections between a host and a storage device
MARVELL INT LTD1 citations48
SILICON STORAGE TECH INC
12 patentsUS11087207B2Aug 10, 2021
Decoders for analog neural memory in deep learning artificial neural network
SILICON STORAGE TECH INC9 citations85
US11423979B2Aug 23, 2022
Decoding system and physical layout for analog neural memory in deep learning artificial neural network
SILICON STORAGE TECH INC5 citations73
US11354562B2Jun 7, 2022
Programmable neuron for analog non-volatile memory in deep learning artificial neural network
SILICON STORAGE TECH INC2 citations73
US10847227B2Nov 24, 2020
Charge pump for use in non-volatile flash memory devices
SILICON STORAGE TECH INC3 citations72
US12579422B2Mar 17, 2026
Input circuitry for analog neural memory in a deep learning artificial neural network
SILICON STORAGE TECH INC0 citations62
US12380932B2Aug 5, 2025
Row decoder and row address scheme in a memory system
SILICON STORAGE TECH INC0 citations62
US12248870B2Mar 11, 2025
Neural network device
SILICON STORAGE TECH INC0 citations62
US12237011B2Feb 25, 2025
Read and programming decoding system for analog neural memory
SILICON STORAGE TECH INC0 citations62
US12099921B2Sep 24, 2024
Decoders for analog neural memory in deep learning artificial neural network
SILICON STORAGE TECH INC0 citations62
US12062397B2Aug 13, 2024
Transceiver for providing high voltages for erase or program operations in a non-volatile memory system
SILICON STORAGE TECH INC0 citations62
US11568229B2Jan 31, 2023
Redundant memory access for rows or columns containing faulty memory cells in analog neural memory in deep learning artificial neural network
SILICON STORAGE TECH INC0 citations62
US11120881B2Sep 14, 2021
Charge pump for use in non-volatile flash memory devices
SILICON STORAGE TECH INC0 citations62
UNISYS CORP
7 patentsUS5386517AJan 31, 1995
Dual bus communication system connecting multiple processors to multiple I/O subsystems having a plurality of I/O devices with varying transfer speeds
UNISYS CORP89 citations94
US5519883AMay 21, 1996
Interbus interface module
UNISYS CORP42 citations91
US5666515ASep 9, 1997
Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address
UNISYS CORP38 citations89
US5706446AJan 6, 1998
Arbitration system for bus requestors with deadlock prevention
UNISYS CORP35 citations87
US5673415ASep 30, 1997
High speed two-port interface unit where read commands suspend partially executed write commands
UNISYS CORP20 citations79
US5644733AJul 1, 1997
Dual coupled partitionable networks providing arbitration logic for managed access to commonly shared busses
UNISYS CORP14 citations68
US5349620ASep 20, 1994
Timer access control apparatus
UNISYS CORP1 citations52
NGUYEN HUY TU
4 patentsUS8156415B1Apr 10, 2012
Method and system for command queuing in disk drives
NGUYEN HUY TU14 citations90
US8566652B1Oct 22, 2013
Command queuing in disk drives
NGUYEN HUY TU6 citations82
US8271701B1Sep 18, 2012
Concurrent input/output control and integrated error management in FIFO
NGUYEN HUY TU10 citations82
US8412895B1Apr 2, 2013
Hard disk controller which coordinates transmission of buffered data with a host
NGUYEN HUY TU1 citations61