Inventor

SOLOMON PAUL M

US106 patents

⚠️ This page may combine multiple inventors who share the name “SOLOMON PAUL M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SOLOMON PAUL M

IBM

Ultra thin body fully-depleted SOI MOSFETs

Method of forming vertical FET with nanowire channels and a silicided bottom contact

Vertical FET with nanowire channels and a silicided bottom contact

Method and apparatus for solution processed doping of carbon nanotube

Method of making a compound semiconductor having metallic inclusions

Compound semiconductor having metallic inclusions and devices fabricated therefrom

Damascene double-gate FET

Method utilizing CMP to fabricate double gate MOSFETS with conductive sidewall contacts

Energy conserving clock pulse generating circuits

Germanium channel silicon MOSFET

Double self-aligned fabrication process for making a bipolar transistor structure having a small polysilicon-to-extrinsic base contact area

Vertical Fet with nanowire channels and a silicided bottom contact

Ultra thin body fully-depleted SOI MOSFETs

Nanowire MOSFET with doped epitaxial contacts for source and drain

Damascene double-gate FET

Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices

Active devices using threads

Two-step MOSFET gate formation for high-density devices

Germanium field effect transistor and method of fabricating the same

BEOL cross-bar array ferroelectric synapse units for domain wall movement

Indirect readout FET

Resistive processing unit weight reading via collection of differential current from first and second memory elements

Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements

Floating gate architecture for deep neural network application

Piezoelectronic memory

Field effect transistor including damascene gate with an internal spacer structure

Self-aligned isolation double-gate FET

Nitride-encapsulated FET (NNCFET)

Field effect transistor with controllable resistance

Method for soft error modeling with double current pulse

Method for protecting refractory metal thin film requiring high temperature processing in an oxidizing atmosphere and structure formed thereby

Saturable charge FET

Staggered bandgap gate field effect transistor

Capacitor based resistive processing unit with symmetric weight update

Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements

Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements

Piezoelectronic device with novel force amplification

Mobile ferroelectric single domain wall implementation of a symmetric resistive processing unit

Symmetric tunable PCM resistor for artificial intelligence circuits

P-N junction based devices with single species impurity for P-type and N-type doping

Intermetallic contact for carbon nanotube FETs

Self-clocked low noise photoreceiver (SCLNP)

SOLOMON PAUL M

Solid state klystron

Solid state klystron

Solid state Klystron

LAUER ISAAC

Fabrication of a vertical heterojunction tunnel-FET

Fabrication of a vertical heterojunction tunnel-FET

FRANKLIN AARON D

Contacts-first self-aligned carbon nanotube transistor with gate-all-around

Contacts-first self-aligned carbon nanotube transistor with gate-all-around

DUBOURDIEU CATHERINE A

Ferroelectric semiconductor transistor devices having gate modulated conductive layer