Inventor

GROCHOWSKI EDWARD T

US78 patents

⚠️ This page may combine multiple inventors who share the name “GROCHOWSKI EDWARD T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GROCHOWSKI EDWARD T

INTEL CORP

Microprocessor with digital power throttle

Microprocessor with dual execution core operable in high reliability mode

Method and apparatus for managing power consumption in a computer system responsive to the power delivery specifications of a power outlet

Method and apparatus of measuring current, voltage, or duty cycle of a power supply to manage power consumption in a computer system

Multiple mode power throttle mechanism

Mechanism to control di/dt for a microprocessor

Branch prediction and resolution apparatus for a superscalar computer processor

Providing extended cache replacement state information

Apparatus and method for reducing power consumption due to cache and TLB accesses in a processor front-end

Processor with sleep and deep sleep modes

Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor

Method of transferring burst data in a microprocessor

Replay mechanism for soft error recovery

Branch prediction and resolution apparatus for a superscalar computer processor

Interruptible and restartable matrix multiplication instructions, processors, methods, and systems

Performing power management in a multicore processor

Systems, apparatuses, and methods for chained fused multiply add

Processor pipeline including replay

Processor pipeline including partial replay

Control of processor pipeline movement through replay queue and pointer backup

Apparatus and method for accessing a split line in a high speed cache

Method of transferring burst data in a microprocessor

Replay mechanism for correcting soft errors

Digital throttle for multiple operating points

Mechanism for estimating and controlling di/dt-induced power supply voltage variations

Predicate prediction based on a predicated predicate value

Method and apparatus for performing predicate prediction

Mechanism for estimating and controlling di/dt-induced power supply voltage variations

Method and apparatus for predicting a predicate based on historical information and the least significant bits of operands to be compared

Method and apparatus for performing predicate prediction

Software-based speculative pre-computation and multithreading

Presbyopic branch target prefetch method and apparatus

Microprocessor with apparatus for parallel execution of instructions

Method and apparatus for dependency checking in a multi-pipelined microprocessor

Systems, methods, and apparatuses for heterogeneous computing

Data element comparison processors, methods, systems, and instructions

Memory-to-memory instructions to accelerate sparse-matrix by dense-vector and sparse-vector by dense-vector multiplication

Static instruction decoder utilizing a circular queue to decode instructions and select instructions to be issued

Systems, apparatuses, and methods for chained fused multiply add

Systems, methods, and apparatuses for heterogeneous computing

Systems, methods, and apparatuses for heterogeneous computing

Zeroing a cache line

Method and apparatus for maintaining cache coherence in a computer system

Using a table to track and locate the latest copy of an operand

Multi-mode microprocessor having a pin for resetting its register without purging its cache

Interruptible and restartable matrix multiplication instructions, processors, methods, and systems

Multiported cache and systems

Systems, methods, and apparatuses for heterogeneous computing

FRYMAN JOSHUA B

Adaptively handling remote atomic execution based upon contention prediction

GROCHOWSKI EDWARD T

Generational thread scheduler using reservations for fair scheduling