Inventor

PIO FEDERICO

IT85 patents

⚠️ This page may combine multiple inventors who share the name “PIO FEDERICO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PIO FEDERICO

ST MICROELECTRONICS SRL

Method of manufacturing double polysilicon EEPROM cell and access transistor

Word line selector for a semiconductor memory

Method for refreshing stored data in an electrically erasable and programmable non-volatile memory

Method of erasing a flash memory

EEPROM memory cell and corresponding manufacturing method

Method of enhancing protection of dielectrics from plasma induced damages and equipment

Array of electrically programmable non-volatile semiconductor memory cells comprising ROM memory cells

Method for saving data in the event of unwanted interruptions in the programming cycle of a nonvolatile memory, and a nonvolatile memory

Double polysilicon EEPROM cell and corresponding manufacturing process and programming method

Memory device with time-shifting based emulation of reference cells

Process for the manufacture of integrated devices with gate oxide protection from manufacturing process damage, and protection structure therefor

Nonvolatile memory test structure and nonvolatile memory reliability test method

Method of manufacturing an integrated semiconductor device having a plurality of connection levels

Electronic structure comprising high and low voltage transistors, and a corresponding fabrication method

Electronic memory circuit and related manufacturing method

Non-volatile memory cell with silicided contacts

Electronic memory circuit and related manufacturing method

Process for forming a non-volatile memory cell with silicided contacts

Method and device for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory device

Method and device for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory device

Process for manufacturing selection transistors for nonvolatile serial-flash, EPROM, EEPROM and flash-EEPROM memories in standard or AMG configuration

Screened EEPROM cell

Method of adjusting program voltage in non-volatile memories, and process for fabricating a non-volatile memory device

Method for programming EEPROM memory devices with improved reliability, and respective EEPROM memory device

MICRON TECHNOLOGY INC

Auto-referenced memory cell read techniques

Method for making three dimensional memory array architecture using phase change and ovonic switching materials

Semiconductor packages with patterns of die-specific information

Auto-referenced memory cell read techniques

Three dimensional memory array architecture

Three dimensional memory array architecture

Semiconductor packages with patterns of die-specific information

Systems and techniques for accessing multiple memory cells concurrently

Systems and techniques for accessing multiple memory cells concurrently

PIO FEDERICO

Three dimensional memory array architecture

Three dimensional memory array architecture

System, apparatus, and reading method for NAND memories

Memory instruction including parameter to affect operating condition of memory

Integrated circuit edge and method to fabricate the same

Exploiting a statistical distribution of the values of an electrical characteristic in a population of auxiliary memory cells for obtaining reference cells

Nonvolatile storage using low latency and high latency memory

SGS THOMSON MICROELECTRONICS

Method for realizing magnetic circuits in an integrated circuit

EEPROM memory cells matrix with double polysilicon level and relating manufacturing process

Circuit structure for a memory matrix and corresponding manufacturing method

Electrically erasable and programmable read-only memory cells with a single polysilicon level and method for producing the same

Method of making thin oxide portions consisting of gate and tunnel oxides particularly in electrically erasable and programmable read-only memory cells

Method of making thin oxide portions particularly in electrically erasable and programmable read-only memory cells

Method of manufacturing a matrix of memory cells having control gates

INTEL CORP

Double-polarity memory read

Double-polarity memory read

MICHELONI RINO

Method for compacting the erased threshold voltage distribution of flash memory devices during writing operations