Inventor

LAJOIE TRAVIS W

US35 patents

Patents

35 patents

US12148734B2Nov 19, 2024

Integrated circuit structures having differentiated interconnect lines in a same dielectric layer

INTEL CORP0 citations62

US11955560B2Apr 9, 2024

Passivation layers for thin film transistors and methods of fabrication

INTEL CORP1 citations62

US11929415B2Mar 12, 2024

Thin film transistors with offset source and drain structures and process for forming such

INTEL CORP0 citations62

US11683929B2Jun 20, 2023

Method for making memory cells based on thin-film transistors

INTEL CORP0 citations62

US12426247B2Sep 23, 2025

Capacitor connections in dielectric layers

INTEL CORP0 citations61

US12150297B2Nov 19, 2024

Thin film transistors having a backside channel contact for high density memory

INTEL CORP0 citations61

US12080781B2Sep 3, 2024

Fabrication of thin film fin transistor structure

INTEL CORP0 citations61

US11991873B2May 21, 2024

Capacitor separations in dielectric layers

INTEL CORP0 citations61

US11832438B2Nov 28, 2023

Capacitor connections in dielectric layers

INTEL CORP0 citations61

US11610894B2Mar 21, 2023

Capacitor separations in dielectric layers

INTEL CORP0 citations61

US12396155B2Aug 19, 2025

Backend memory with air gaps in upper metal layers

INTEL CORP0 citations60

US12513970B2Dec 30, 2025

Integrated circuits with tungsten interconnect liners

INTEL CORP0 citations59

US11563107B2Jan 24, 2023

Method of contact patterning of thin film transistors for embedded DRAM using a multi-layer hardmask

INTEL CORP0 citations59

US12490460B2Dec 2, 2025

Dielectric sidewall features for tuning thin film transistor (TFT) parasitics

INTEL CORP0 citations58

US12444678B2Oct 14, 2025

Spacer-based self-aligned interconnect features

INTEL CORP0 citations57

US12476183B2Nov 18, 2025

Punch-through interconnect feature to couple upper electrodes of capacitors of multi-level memory arrays

INTEL CORP0 citations56

US12599032B2Apr 7, 2026

Bilayer memory stacking with lines shared between bottom and top memory layers

INTEL CORP0 citations52

US12512409B2Dec 30, 2025

Hybrid etch stop layers

INTEL CORP0 citations52

US11574910B2Feb 7, 2023

Device with air-gaps to reduce coupling capacitance and process for forming such

INTEL CORP0 citations52

US11450669B2Sep 20, 2022

Stacked thin-film transistor based embedded dynamic random-access memory

INTEL CORP0 citations52

US12564035B2Feb 24, 2026

Airgaps used in backend memory structures

INTEL CORP0 citations51

US11404536B2Aug 2, 2022

Thin-film transistor structures with gas spacer

INTEL CORP0 citations51

US12446208B2Oct 14, 2025

Multilevel wordline assembly for embedded DRAM

INTEL CORP0 citations50

US11950407B2Apr 2, 2024

Memory architecture with shared bitline at back-end-of-line

INTEL CORP0 citations50

US11652047B2May 16, 2023

Intermediate separation layers at the back-end-of-line

INTEL CORP0 citations50

US12176147B2Dec 24, 2024

Three-dimensional capacitors with double metal electrodes

INTEL CORP0 citations45

US12588241B2Mar 24, 2026

Asymmetric source and drain contacts for a thin film transistor (TFT) structure

INTEL CORP0 citations43

LAJOIE TRAVIS W

Patents

Transistors, memory cells, and arrangements thereof

Memory cells based on vertical thin-film transistors

Thin-film transistor embedded dynamic random-access memory with shallow bitline

Memory cells based on thin-film transistors

Thin-film transistor embedded dynamic random-access memory with shallow bitline

Two transistor memory cell using stacked thin-film transistors

Passivation layers for thin film transistors

Decoupling capacitors and methods of fabrication

Integrated circuit structures having differentiated interconnect lines in a same dielectric layer

Passivation layers for thin film transistors and methods of fabrication

Thin film transistors with offset source and drain structures and process for forming such

Method for making memory cells based on thin-film transistors

Capacitor connections in dielectric layers

Thin film transistors having a backside channel contact for high density memory

Fabrication of thin film fin transistor structure

Capacitor separations in dielectric layers

Capacitor connections in dielectric layers

Capacitor separations in dielectric layers

Backend memory with air gaps in upper metal layers

Integrated circuits with tungsten interconnect liners

Method of contact patterning of thin film transistors for embedded DRAM using a multi-layer hardmask

Dielectric sidewall features for tuning thin film transistor (TFT) parasitics

Spacer-based self-aligned interconnect features

Punch-through interconnect feature to couple upper electrodes of capacitors of multi-level memory arrays

Bilayer memory stacking with lines shared between bottom and top memory layers

Hybrid etch stop layers

Device with air-gaps to reduce coupling capacitance and process for forming such

Stacked thin-film transistor based embedded dynamic random-access memory

Airgaps used in backend memory structures

Thin-film transistor structures with gas spacer

Multilevel wordline assembly for embedded DRAM

Memory architecture with shared bitline at back-end-of-line

Intermediate separation layers at the back-end-of-line

Three-dimensional capacitors with double metal electrodes

Asymmetric source and drain contacts for a thin film transistor (TFT) structure