Inventor
ALZATE VINASCO JUAN G
US21 patents
Patents
21 patentsUS11462541B2Oct 4, 2022
Memory cells based on vertical thin-film transistors
INTEL CORP2 citations73
US10832749B2Nov 10, 2020
Perpendicular magnetic memory with symmetric fixed layers
INTEL CORP5 citations73
US11758711B2Sep 12, 2023
Thin-film transistor embedded dynamic random-access memory with shallow bitline
INTEL CORP2 citations72
US11329047B2May 10, 2022
Thin-film transistor embedded dynamic random-access memory with shallow bitline
INTEL CORP4 citations72
US11063088B2Jul 13, 2021
Magnetic memory devices and methods of fabrication
INTEL CORP3 citations69
US12238913B2Feb 25, 2025
Two transistor memory cell using stacked thin-film transistors
INTEL CORP1 citations64
US12310001B2May 20, 2025
Decoupling capacitors and methods of fabrication
INTEL CORP1 citations62
US12080643B2Sep 3, 2024
Integrated circuit structures having differentiated interconnect lines in a same dielectric layer
INTEL CORP0 citations62
US10365894B2Jul 30, 2019
Random number generator
INTEL CORP1 citations62
US12426247B2Sep 23, 2025
Capacitor connections in dielectric layers
INTEL CORP0 citations61
US11991873B2May 21, 2024
Capacitor separations in dielectric layers
INTEL CORP0 citations61
US11832438B2Nov 28, 2023
Capacitor connections in dielectric layers
INTEL CORP0 citations61
US11690212B2Jun 27, 2023
Memory architecture at back-end-of-line
INTEL CORP0 citations61
US11610894B2Mar 21, 2023
Capacitor separations in dielectric layers
INTEL CORP0 citations61
US12513970B2Dec 30, 2025
Integrated circuits with tungsten interconnect liners
INTEL CORP0 citations59
US11616192B2Mar 28, 2023
Magnetic memory devices with a transition metal dopant at an interface of free magnetic layers and methods of fabrication
INTEL CORP0 citations57
US12599032B2Apr 7, 2026
Bilayer memory stacking with lines shared between bottom and top memory layers
INTEL CORP0 citations52
US11450669B2Sep 20, 2022
Stacked thin-film transistor based embedded dynamic random-access memory
INTEL CORP0 citations52
US12446208B2Oct 14, 2025
Multilevel wordline assembly for embedded DRAM
INTEL CORP0 citations50
US11950407B2Apr 2, 2024
Memory architecture with shared bitline at back-end-of-line
INTEL CORP0 citations50
US11652047B2May 16, 2023
Intermediate separation layers at the back-end-of-line
INTEL CORP0 citations50