Inventor

SILBERMAN JOEL A

US41 patents

⚠️ This page may combine multiple inventors who share the name “SILBERMAN JOEL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SILBERMAN JOEL A

IBM

Method and system for restoring register mapper states for an out-of-order microprocessor

Method and apparatus for performing add and rotate as a single instruction within a processor

Counter-flow expanding channels for enhanced two-phase heat removal

High cutoff frequency metal-insulator-metal capacitors implemented using via contact configurations

Scannable latch

Active control for two-phase cooling

Instruction fusion after register rename

Scalable dependency matrix with multiple summary bits in an out-of-order processor

Active control for two-phase cooling

Active control for two-phase cooling

Counter-flow expanding channels for enhanced two-phase heat removal

Active control for two-phase cooling

Coalescing global completion table entries in an out-of-order processor

Completing coalesced global completion table entries in an out-of-order processor

Hybrid extremely thin silicon-on-insulator (ETSOI) structure to minimize noise coupling from TSV

Programmable logic array latch

Instruction selection mechanism with class-dependent age-array

Scalable dependency matrix with a single summary bit in an out-of-order processor

Issue queue with dynamic shifting between ports

Coalescing global completion table entries in an out-of-order processor

3D integrated circuit stack-wide synchronization circuit

Scannable latch

Half-precision floating-point arrays at low overhead

Counter-flow expanding channels for enhanced two-phase heat removal

Counter-flow expanding channels for enhanced two-phase heat removal

Hybrid ETSOI structure to minimize noise coupling from TSV

Hybrid ETSOI structure to minimize noise coupling from TSV

Head and tail pointer manipulation in a first-in-first-out issue queue

Block based allocation and deallocation of issue queue entries

Buffered instruction dispatching to an issue queue

Scalable dependency matrix with wake-up columns for long latency instructions in an out-of-order processor

Apparatus and method for power savings in high-performance CAM structures

KIM JAE-JOON

3D chip stack skew reduction with resonant clock and inductive coupling

AC supply noise reduction in a 3D stack with voltage sensing and clock shifting

3D chip stack skew reduction with resonant clock and inductive coupling

PANG LIANG-TECK

Programming the behavior of individual chips or strata in a 3D stack of integrated circuits

Programming the behavior of individual chips or strata in a 3D stack of integrated circuits

SCHEUERMANN MICHAEL R

Configuration of connections in a 3D stack of integrated circuits

ISLAM SAIFUL

Dependency matrix with reduced area and power consumption

SILBERMAN JOEL A

3D integrated circuit stack-wide synchronization circuit

DUAN XIAOMIN

Through silicon via noise suppression using buried interface contacts