Inventor
RIGGS EILEEN
US4 patents
Patents
4 patentsUS5345576ASep 6, 1994
Microprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache miss
INTEL CORP54 citations91
US5276690AJan 4, 1994
Apparatus utilizing dual compare logic for self checking of functional redundancy check (FRC) logic
INTEL CORP60 citations91
US4903270AFeb 20, 1990
Apparatus for self checking of functional redundancy check (FRC) logic
INTEL CORP34 citations91
US5050066ASep 17, 1991
Apparatus with a single memory and a plurality of queue counters for queuing requests and replies on a pipelined packet bus
INTEL CORP45 citations90