Inventor
SALYER GREGORY
US12 patents
⚠️ This page may combine multiple inventors who share the name “SALYER GREGORY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
11 patentsUS5265232ANov 23, 1993
Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data
IBM121 citations95
US5548623AAug 20, 1996
Null words for pacing serial links to driver and receiver speeds
IBM22 citations92
US5509122AApr 16, 1996
Configurable, recoverable parallel bus
IBM34 citations92
US5455831AOct 3, 1995
Frame group transmission and reception for parallel/serial buses
IBM50 citations92
US5412803AMay 2, 1995
Communications system having plurality of originator and corresponding recipient buffers with each buffer having three different logical areas for transmitting messages in single transfer
IBM35 citations92
US5357608AOct 18, 1994
Configurable, recoverable parallel bus
IBM42 citations92
US5267240ANov 30, 1993
Frame-group transmission and reception for parallel/serial buses
IBM19 citations81
US7552232B2Jun 23, 2009
Speculative method and system for rapid data communications
IBM13 citations80
US5418939AMay 23, 1995
Concurrent maintenance of degraded parallel/serial buses
IBM15 citations73
US5680575AOct 21, 1997
Interconnect failure detection and cache reset apparatus
IBM10 citations68
US4635186AJan 6, 1987
Detection and correction of multi-chip synchronization errors
IBM16 citations68