Inventor

RAZDAN RAHUL

US27 patents

⚠️ This page may combine multiple inventors who share the name “RAZDAN RAHUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAZDAN RAHUL

DIGITAL EQUIPMENT CORP

Determining hardware complexity of software operations

Dynamically programmable reduced instruction set computer with programmable processor loading on program number field and program number register contents

Method and apparatus for maximizing utilization of an internal processor bus in the context of external transactions running at speeds fractionally greater than internal transaction times

High capacity netlist comparison

Method and apparatus for minimizing pincount needed by external memory control chip for multiprocessors with limited memory size requirements

Using pre-analysis and a 2-state optimistic model to reduce computation in transistor circuit simulation

Simulation of circuits

COMPAQ INFORMATION TECHNOLOGIE

Method and apparatus for delaying the execution of dependent loads

Method and apparatus for performing speculative memory fills into a microprocessor

Method and apparatus for developing multiprocessor cache control protocols by presenting a clean victim signal to an external system

Method and apparatus for resolving probes in multi-processor systems which do not use external duplicate tags for probe filtering

Methods and apparatus for minimizing the impact of excessive instruction retrieval

Method and apparatus for developing multiprocessor cache control protocols using a memory management system generating atomic probe commands and system data control response commands

Method and apparatus for optimizing bcache tag performance by inferring bcache tag state from internal processor state

COMPAQ COMPUTER CORP

Distributed data dependency stall mechanism

Distributed data dependency stall mechanism

Method and apparatus for minimizing dcache index match aliasing using hashing in synonym/subset processing

Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol

Method and apparatus for developing multiprocessor cache control protocols using atomic probe commands and system data control response commands

Method and apparatus for a dedicated physically indexed copy of the data cache tag arrays

MICROSOFT TECHNOLOGY LICENSING LLC

Smart search for annotations and inking

Selective consumption of web page data over a data-limited connection

Shared knowledge about contents

CADENCE DESIGN SYSTEMS INC

Method and apparatus for critical and false path verification

Method and apparatus for enhancing the performance of event driven dynamic simulation of digital circuits based on netlist partitioning techniques

HARVARD COLLEGE

Hardware extraction technique for programmable reduced instruction set computers

HEWLETT PACKARD DEVELOPMENT CO

Method and apparatus for developing multiprocessor cache control protocols using an external acknowledgement signal to set a cache to a dirty state