Inventor
JORDAN PAUL JOSEPH
US11 patents
Patents
11 patentsUS6701484B1Mar 2, 2004
Register file with delayed parity check
IBM24 citations92
US6658534B1Dec 2, 2003
Mechanism to reduce instruction cache miss penalties and methods therefor
IBM28 citations92
US6061777AMay 9, 2000
Apparatus and method for reducing the number of rename registers required in the operation of a processor
IBM25 citations92
US5974524AOct 26, 1999
Method and apparatus for reducing the number of rename registers in a processor supporting out-of-order execution
IBM46 citations92
US5805849ASep 8, 1998
Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions
IBM36 citations92
US5805906ASep 8, 1998
Method and apparatus for writing information to registers in a data processing system using a number of registers for processing instructions
IBM20 citations92
US6629170B1Sep 30, 2003
Method and apparatus for a byte lane selectable performance monitor bus
IBM15 citations83
US5875326AFeb 23, 1999
Data processing system and method for completing out-of-order instructions
IBM16 citations73
US6336182B1Jan 1, 2002
System and method for utilizing a conditional split for aligning internal operation (IOPs) for dispatch
IBM11 citations72
US5999992ADec 7, 1999
System and method for controlling the direction of data flow between computing elements
IBM11 citations65
US5983341ANov 9, 1999
Data processing system and method for extending the time for execution of an instruction
IBM4 citations62