Inventor

KRAMER DAVID B

US34 patents

⚠️ This page may combine multiple inventors who share the name “KRAMER DAVID B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KRAMER DAVID B

AGERE SYSTEMS INC

Virtual reassembly system and method of operation thereof

Processor architecture and a method of processing

Processor with table-based scheduling using software-controlled interval computation

Processor with software-controlled programmable service levels

Processor with scheduler architecture supporting multiple distinct scheduling algorithms

Virtual reassembly system and method of operation thereof

Virtual segmentation system and method of operation thereof

Processor with dynamic table-based scheduling using linked transmission elements for handling transmission request collisions

Processor with dynamic table-based scheduling using multi-entry table locations for handling transmission request collisions

Virtual segmentation system and method of operation thereof

Link layer device with non-linear polling of multiple physical layer device ports

Link layer device with configurable address pin allocation

XU KUN

System and method for assigning memory access transfers between communication channels

Message passing using direct memory access unit in a data processing system

Asynchronously scheduling memory access requests

System and method for scalable movement and replication of data

Bandwidth control for a direct memory access unit within a data processing system

Scheduling memory access requests using predicted memory timing and state information

Controller for managing a reset of a subset of threads in a multi-thread system

MARIETTA BRYAN D

Method and apparatus for determining access permissions in a partitioned data processing system

Interrupt priority management using partition-based priority blocking processor registers

Processor interrupt interface with interrupt partitioning and virtualization enhancements

Virtualized instruction extensions for system partitioning

Virtualized interrupt delay mechanism

JOKINEN TOMMI M

System and method for maintaining packet order in an ordered data stream

System and method for direct memory access buffer utilization by setting DMA controller with plurality of arbitration weights associated with different DMA engines

System and method for transferring data between components of a data processor

System and method for conditional task switching during ordering scope transitions

FREESCALE SEMICONDUCTOR INC

Non-volatile RAM system

System and method for implementing ACLs using standard LPM engine

System and method for assigning a message

CISCO TECH INC

Locking mechanism for rack mounted devices

KRAMER DAVID B

Configurable peripheral componenent interconnect express (PCIe) controller

HOLT JAMES C

Explicit barrier scheduling mechanism for pipelining of stream processing algorithms