Inventor

GRAIF SHARON

IL25 patents

⚠️ This page may combine multiple inventors who share the name “GRAIF SHARON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GRAIF SHARON

QUALCOMM INC

Low latency virtual general purpose input/output over I3C

High bandwidth soundwire master with multiple primary data lanes

Extended current limit message latency aware performance mitigation

Slave-to-slave direct communication

I3C read from long latency devices

Fast activation during wake up in an audio system

I2C bus architecture using shared clock and dedicated data lines

Fast termination of multilane single data rate transactions

High-speed communication link with self-aligned scrambling

High-speed communication link with self-aligned scrambling

Group slave identifier time-multiplexed acknowledgment for system power management interface

Aggregated in-band interrupt based on responses from slave devices on a serial data bus line

Hang correction in a power management interface bus

Bus ownership for a system power management interface (SPMI) bus

Virtual general purpose input/output (GPIO) (VGI) over a time division multiplex (TDM) bus

Scrambling data-port audio in SOUNDWIRE systems

Bus controller and related methods

In-system structural testing of a system-on-chip (SoC) using a peripheral interface port

I3C point to point

Urgent in-band interrupts on an I3C bus

Providing acknowledgements for system power management interface

Phase alignment in an audio bus

Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media

Latency optimized I3C virtual GPIO with configurable operating mode and device skip

REINHARDT STEFFEN

Scalable DigRF architecture