Inventor
BCHIR OMAR J
US19 patents
⚠️ This page may combine multiple inventors who share the name “BCHIR OMAR J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
QUALCOMM INC
4 patentsUS8368232B2Feb 5, 2013
Sacrificial material to facilitate thin die attach
QUALCOMM INC8 citations83
US9269681B2Feb 23, 2016
Surface finish on trace for a thermal compression flip chip (TCFC)
QUALCOMM INC4 citations70
US9461008B2Oct 4, 2016
Solder on trace technology for interconnect attachment
QUALCOMM INC2 citations62
US8802556B2Aug 12, 2014
Barrier layer on bump and non-wettable coating on trace
QUALCOMM INC2 citations59
MICRON TECHNOLOGY INC
4 patentsUS11024617B2Jun 1, 2021
Semiconductor packages having photon integrated circuit (PIC) chips
MICRON TECHNOLOGY INC3 citations72
US10928585B2Feb 23, 2021
Semiconductor devices having electro-optical substrates
MICRON TECHNOLOGY INC3 citations72
US12300680B2May 13, 2025
Semiconductor packages having photon integrated circuit (PIC) chips
MICRON TECHNOLOGY INC0 citations62
US11525956B2Dec 13, 2022
Semiconductor devices having electro-optical substrates
MICRON TECHNOLOGY INC1 citations62
INTEL CORP
4 patentsUS7923059B2Apr 12, 2011
Method of enabling selective area plating on a substrate
INTEL CORP2 citations62
US7432202B2Oct 7, 2008
Method of substrate manufacture that decreases the package resistance
INTEL CORP4 citations58
US8017022B2Sep 13, 2011
Selective electroless plating for electronic substrates
INTEL CORP1 citations51
US7727886B2Jun 1, 2010
Forming vias using sacrificial material
INTEL CORP1 citations51
BCHIR OMAR J
3 patentsUS7583871B1Sep 1, 2009
Substrates for optical die structures
BCHIR OMAR J8 citations81
US8742603B2Jun 3, 2014
Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC)
BCHIR OMAR J1 citations44
US8703602B2Apr 22, 2014
Selective seed layer treatment for feature plating
BCHIR OMAR J0 citations44