Inventor
HECHT VOLKER
DE29 patents
⚠️ This page may combine multiple inventors who share the name “HECHT VOLKER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ACTEL CORP
15 patentsUS7884640B2Feb 8, 2011
PLD providing soft wakeup logic
ACTEL CORP9 citations84
US6272655B1Aug 7, 2001
Method of reducing test time for NVM cell-based FPGA
ACTEL CORP15 citations82
US6777977B1Aug 17, 2004
Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop
ACTEL CORP12 citations79
US7932745B2Apr 26, 2011
Inverting flip-flop for use in field programmable gate arrays
ACTEL CORP6 citations74
US7816946B1Oct 19, 2010
Inverting flip-flop for use in field programmable gate arrays
ACTEL CORP6 citations74
US7212030B1May 1, 2007
Field programmable gate array long line routing network
ACTEL CORP5 citations73
US7365567B2Apr 29, 2008
Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop
ACTEL CORP6 citations71
US7106100B1Sep 12, 2006
Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop
ACTEL CORP4 citations71
US7919977B2Apr 5, 2011
Circuits and methods for testing FPGA routing switches
ACTEL CORP2 citations63
US7804321B2Sep 28, 2010
Circuits and methods for testing FPGA routing switches
ACTEL CORP2 citations63
US7522453B1Apr 21, 2009
Non-volatile memory with source-side column select
ACTEL CORP3 citations63
US7161841B1Jan 9, 2007
Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage
ACTEL CORP4 citations63
US7394286B2Jul 1, 2008
Field programmable gate array long line routing network
ACTEL CORP2 citations62
US7593268B2Sep 22, 2009
Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage
ACTEL CORP0 citations52
US7477071B2Jan 13, 2009
Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop
ACTEL CORP0 citations49
MICROSEMI SOC CORP
7 patentsUS9704573B1Jul 11, 2017
Three-transistor resistive random access memory cells
MICROSEMI SOC CORP13 citations84
US10523208B2Dec 31, 2019
Efficient lookup table modules for user-programmable integrated circuits
MICROSEMI SOC CORP2 citations73
US10147485B2Dec 4, 2018
Circuits and methods for preventing over-programming of ReRAM-based memory cells
MICROSEMI SOC CORP2 citations73
US9103880B2Aug 11, 2015
On-chip probe circuit for detecting faults in an FPGA
MICROSEMI SOC CORP2 citations60
US9000807B2Apr 7, 2015
On-chip probe circuit for detecting faults in an FPGA
MICROSEMI SOC CORP3 citations60
US11031078B2Jun 8, 2021
SEU stabilized memory cells
MICROSEMI SOC CORP0 citations50
US9990993B2Jun 5, 2018
Three-transistor resistive random access memory cells
MICROSEMI SOC CORP0 citations42
GATEFIELD CORP
3 patentsUS6125059ASep 26, 2000
Method for erasing nonvolatile memory cells in a field programmable gate array
GATEFIELD CORP24 citations92
US6072720AJun 6, 2000
Nonvolatile reprogrammable interconnect cell with programmable buried bitline
GATEFIELD CORP16 citations82
US6137728AOct 24, 2000
Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor
GATEFIELD CORP14 citations72