Inventor

MURRAY CONAL E

US69 patents

⚠️ This page may combine multiple inventors who share the name “MURRAY CONAL E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MURRAY CONAL E

IBM

Treating copper interconnects

Activating reactions in integrated circuits through electrical discharge

Semiconductor device with reduced via resistance

Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process

Method and structure for reducing contact resistance between silicide contact and overlying metallization

Reprogrammable electrical fuse

Heat dissipation for heat generating element of semiconductor device and related method

Building metal pillars in a chip for structure support

Stacked via-stud with improved reliability in copper metallurgy

Semiconductor device with reduced via resistance

Semiconductor device with reduced via resistance

Method for forming improved liner layer and semiconductor device including the same

Hybrid interconnects and method of forming the same

Varying capacitance voltage contrast structures to determine defect resistance

Method and structure for reducing contact resistance between silicide contact and overlying metallization

Interconnect structure and method for Cu/ultra low k integration

Process for preparing electronics structures using a sacrificial multilayer hardmask scheme

Apparatus and method for flattening a warped substrate

Building metal pillars in a chip for structure support

Reducing contact resistance in vias for copper interconnects

Reducing contact resistance in vias for copper interconnects

Forming a stacked capacitor

Semiconductor device interconnect structures formed by metal reflow process

Eliminating metal-rich silicides using an amorphous Ni alloy silicide structure

Capacitance monitoring using X-ray diffraction

Electronics structures using a sacrificial multi-layer hardmask scheme

Forming a stacked capacitor

Activating reactions in integrated circuits through electrical discharge

Carbon-on-insulator substrates by in-place bonding

Structure for optimizing fill in semiconductor features deposited by electroplating

Deflection analysis system and method for circuit design

Method of determining stopping powers of design structures with respect to a traveling particle

Eliminating metal-rich silicides using an amorphous Ni alloy silicide structure

Method for SEM measurement of topological features

HSU LOUIS L

Air channel interconnects for 3-D integration

Redundancy design with electro-migration immunity

Redundancy design with electro-migration immunity and method of manufacture

Redundancy design with electro-migration immunity and method of manufacture

BANGSARUNTIP SARUNYA

Nanowire FET having induced radial strain

Nanowire FET having induced radial strain

Nanowire FET having induced radial strain

COHEN GUY

p-FET with a strained nanowire channel and embedded SiGe source and drain stressors

p-FET with a strained nanowire channel and embedded SiGe source and drain stressors

CABRAL JR CYRIL

Dosimeter powered by passive RF absorption

Annealing copper interconnects

HSU LOUIS C

Reprogrammable electrical fuse

TESSERA LLC

Semiconductor device with reduced via resistance

TESSERA INC

Semiconductor device with reduced via resistance

YANG CHIH-CHAO

Interconnect structure and method for Cu/ultra low k integration

INTERNATIONIAL BUSINESS MACHIN

Eliminating metal-rich silicides using an amorphous Ni alloy silicide structure