Inventor

JAYAKUMAR SARATHY

US43 patents

⚠️ This page may combine multiple inventors who share the name “JAYAKUMAR SARATHY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAYAKUMAR SARATHY

INTEL CORP

Controlling memory redundancy in a system

Providing dedicated resources for a system management mode of a processor

Computing platform with interface based error injection

Computing platform performance management with RAS services

Techniques to communicate with a controller for a non-volatile dual in-line memory module

Update of boot code handlers

Fast memory initialization

Apparatus and method to identify the source of an interrupt

Apparatus and method for fast cache flushing including determining whether data is to be stored in nonvolatile memory

CPU hot-swapping

Systems and method for dynamic address based mirroring

Deployment of BIOS to operating system data exchange

Read from memory instructions, processors, methods, and systems, that do not take exception on defective data

Computing platform interface with memory management

Execution context migration method and apparatus

Computing platform interface with memory management

Methods and apparatus for generating system management interrupts

Apparatus and method to identify the source of an interrupt

Apparatus and method to identify the source of an interrupt

Protected runtime mode

Delayed error processing

Computing platform with interface based error injection

Decoupling silicon initialization and bootloader by providing silicon initialization service

Methods and apparatus to perform a pseudo-S3 protocol to update firmware and/or activate new firmware with a warm reset

Seamless SMM global driver update base on SMM root of trust

Firmware first handling of a machine check event

Modular microcode (uCode) patch method to support runtime persistent update

Arbiter based serialization of processor system management interrupt events

Firmware-related event notification

Computing platform interface with memory management

Firmware-related event notification

Firmware assisted error handling scheme

Read from memory instructions, processors, methods, and systems, that do not take exception on defective data

Apparatus and method for system physical address to memory module address translation

Hardware unit for reverse translation in a processor

Technologies for secure and efficient native code invocation for firmware services

Microcode(uCode) hot-upgrade method for bare metal cloud deployment

JAYAKUMAR SARATHY

Recovery after input/ouput error-containment events

Logic device having status and control registers for recording the status and controlling the operation of memory slots such that each memory slot is identified using a bus address and port number

System management interrupt handling for multi-core processors

Bi-directional handshake for advanced reliabilty availability and serviceability

SWANSON ROBERT C

Controlling memory redundancy in a system

KUMAR MOHAN

Firmware assisted error handling scheme