Inventor

ASHER DAVID H

US20 patents

⚠️ This page may combine multiple inventors who share the name “ASHER DAVID H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ASHER DAVID H

HEWLETT PACKARD DEVELOPMENT CO

Scalable directory based cache coherence protocol

Mechanism to control the allocation of an N-source shared buffer

Fast lane prefetching

Method for reducing directory writes and latency in a high performance, directory-based, coherency protocol

Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache

Scalable directory based cache coherence protocol

Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache

CAVIUM INC

Input output bridging

Inter-chip interconnect protocol for a multi-chip system

Method and apparatus for conditional storing of data using a compare-and-swap based approach

Method and apparatus for managing write back cache

MARVELL ASIA PTE LTD

Shared mid-level data cache

Mid-level instruction cache

Processor data cache with shared mid-level cache and low-level cache

CAVIUM NETWORKS INC

Store instruction ordering for multi-core processor

Local scratchpad and data caching system

COMPAQ COMPUTER CORP

Profile directed simulation used to target time-critical crossproducts during random vector testing

SANZONE ROBERT A

Input output bridging

DOBBIE BRADLEY D

Network processor with distributed trace buffers

KESSLER RICHARD E

Multi-core interconnect in a network processor