Inventor

SINHA DEBJIT

US36 patents

⚠️ This page may combine multiple inventors who share the name “SINHA DEBJIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SINHA DEBJIT

IBM

System and method for maintaining slack continuity in incremental statistical timing analysis

Performing statistical timing analysis with non-separable statistical and deterministic variations

Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis

Method of constrained aggressor set selection for crosstalk induced noise

Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertions

Multi-sided variations for creating integrated circuits

Incremental common path pessimism analysis

Prioritized path tracing in statistical timing analysis of integrated circuits

Parallel access to running electronic design automation (EDA) application

Statistical timing using macro-model considering statistical timing value entry

Apportionment aware hierarchical timing optimization

Efficient projection based adjustment evaluation in static timing analysis of integrated circuits

Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs

Device-based random variability modeling in timing analysis

Statistical timing analysis considering multiple-input switching

Parallel access to running electronic design automation (EDA) application

Multi-sided variations for creating integrated circuits

Multi-sided variations for creating integrated circuits

Method of sharing and re-using timing models in a chip across multiple voltage domains

Incremental common path pessimism analysis

Accurate statistical timing for boundary gates of hierarchical timing models

Accurate statistical timing for boundary gates of hierarchical timing models

Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints

Distributed timing analysis of a partitioned integrated circuit design

Variation-aware timing analysis using waveform construction

Variable accuracy incremental timing analysis

Deterministic and statistical timing modeling for differential circuits

SINHA DEBJIT

Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits

Method of performing timing analysis on integrated circuit chips with consideration of process variations

Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits

Method and apparatus for efficient incremental statistical timing analysis and optimization

HEMMETT JEFFREY G

Performing statistical timing analysis with non-separable statistical and deterministic variations

BUCK NATHAN

Statistical clock cycle computation

FOREMAN ERIC A

Efficient slack projection for truncated distributions

ABBASPOUR SOROUSH

Method of performing static timing analysis considering abstracted cell&#39;s interconnect parasitics

VISWESWARIAH CHANDRAMOULI

Method for achieving an efficient statistical optimization of integrated circuits

Method of performing static timing analysis considering abstracted cell's interconnect parasitics