Inventor

ABBASPOUR SOROUSH

US17 patents

⚠️ This page may combine multiple inventors who share the name “ABBASPOUR SOROUSH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ABBASPOUR SOROUSH

IBM

Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits

Method and apparatus for static timing analysis in the presence of a coupling event and process variation

Multiple voltage threshold timing analysis for a digital integrated circuit

Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis

Method of constrained aggressor set selection for crosstalk induced noise

Method for incorporating Miller capacitance effects in digital circuits for an accurate timing analysis

Arbitrary waveform propagation through a logic gate using timing analysis results

Integrated circuit (IC) chip design method, program product and system

Moment-based characterization waveform for static timing analysis

ABBASPOUR SOROUSH

Method of performing static timing analysis considering abstracted cell&#39;s interconnect parasitics

Order independent method of performing statistical N-way maximum/minimum operation for non-Gaussian and non-linear distributions

Efficient compression and handling of model library waveforms

Method and system for optimizing a device with current source models

Performing reliability analysis of signal wires

SINHA DEBJIT

Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits

BANERJI REVANTA

Method for supporting multiple libraries characterized at different process, voltage and temperature points

FELDMANN PETER

Characterization of nonlinear cell macro model for timing analysis

Method of performing static timing analysis considering abstracted cell's interconnect parasitics