Inventor

BHANJI ADIL

US10 patents

⚠️ This page may combine multiple inventors who share the name “BHANJI ADIL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

7 patents

US7788617B2Aug 31, 2010

Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis

IBM12 citations83

US10970455B1Apr 6, 2021

Apportionment aware hierarchical timing optimization

IBM3 citations69

US10831954B1Nov 10, 2020

Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs

IBM2 citations66

US9607124B2Mar 28, 2017

Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints

IBM1 citations51

US10169503B2Jan 1, 2019

SINHA DEBJIT

2 patents

US8122404B2Feb 21, 2012

Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits

SINHA DEBJIT15 citations82

US8103997B2Jan 24, 2012

Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits

SINHA DEBJIT6 citations69

BHANJI ADIL

1 patent

US8185371B2May 22, 2012

Modeling full and half cycle clock variability

BHANJI ADIL0 citations24

BHANJI ADIL

IBM

Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis

Apportionment aware hierarchical timing optimization

Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs

Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints

Callback based constraint processing for clock domain independence

Callback based constraint processing for clock domain independence

Clock domain-independent abstracts

SINHA DEBJIT

Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits

Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits

BHANJI ADIL

Modeling full and half cycle clock variability