Inventor

DE SOUZA JOEL P

US128 patents

⚠️ This page may combine multiple inventors who share the name “DE SOUZA JOEL P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DE SOUZA JOEL P

IBM

Semiconductor chip having tampering feature

Defect induced buried oxide (DIBOX) for throughput SOI

Reduction of defect induced leakage in III-V semiconductor devices

Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer

Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal

Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal

Rechargeable lithium-ion battery with an anode structure containing a porous region

High charge rate, large capacity, solid-state battery

Fabrication method of all solid-state thin-film battery

Silicon germanium-on-insulator formation by thermal mixing

MOSFET with ultra low drain leakage

Three-terminal non-volatile multi-state memory for cognitive computing applications

Semiconductor chip having tampering feature

Leakage-free implantation-free ETSOI transistors

Reduction of defect induced leakage in III-V semiconductor devices

MOSFET with ultra low drain leakage

Strained semiconductor-on-insulator (sSOI) by a simox method

Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers

Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost

Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same

Dual SIMOX hybrid orientation technology (HOT) substrates

Surface treatment of textured silicon

Strained semiconductor-on-insulator (sSOI) by a simox method

Defect induced buried oxide (DIBOX) for throughput SOI

Silicon substrate containing integrated porous silicon electrodes for energy storage devices

MOSFET with ultra low drain leakage

Battery structure with stable voltage for neuromorphic computing

Leakage-free implantation-free ETSOI transistors

Battery structure with an anode structure containing a porous region and method of operation

Low-cost SOI FinFET technology

Interface charge reduction for SiGe surface

Indium gallium arsenide metal oxide semiconductor field effect transistor having a low contact resistance to metal electrode

Surface passivation having reduced interface defect density

Low-cost SOI FinFET technology

Self-aligned source and drain regions for semiconductor devices

Junction interlayer dielectric for reducing leakage current in semiconductor devices

Doped zinc oxide and n-doping to reduce junction leakage

Local SOI fins with multiple heights

Self-aligned source and drain regions for semiconductor devices

Method for internal gettering of oxygen in iii-v compound semiconductors

Internal gettering of oxygen in III-V compound semiconductors

Phase-change memory (PCM) including liner reducing resistance drift

Battery-based neural network weights

Leakage-free implantation-free ETSOI transistors

DE SOUZA JOEL P

Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide

Device and method for boron diffusion in semiconductors

Strain preserving ion implantation methods

Method to prevent surface decomposition of III-V compound semiconductors

GLOBALFOUNDRIES INC

Method and structure to make fins with different fin heights and no topography

Low defect III-V semiconductor template on porous silicon