Inventor

CHUANG PATRICK

US25 patents

⚠️ This page may combine multiple inventors who share the name “CHUANG PATRICK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHUANG PATRICK

GSI TECHNOLOGY INC

Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits

Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry

Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry

Memory systems and methods involving high speed local address circuitry

Systems and methods involving lock loop circuits, distributed duty cycle correction loop circuitry

Systems and methods involving pseudo complementary output buffer circuitry/schemes, power noise reduction and/or other features

Systems and methods involving multi-bank, dual- or multi-pipe SRAMs

Memory systems and methods involving high speed local address circuitry

Systems and methods involving multi-bank, dual- or multi-pipe SRAMs

Ultra low VDD memory cell with ratioless write port

Computational memory cell and processing array device with ratioless write port

Results processing circuits and methods associated with computational memory cells

Orthogonal data transposition system and method during data transfers to/from a processing array

Systems and methods involving multi-bank, dual-pipe memory circuitry

Orthogonal data transposition system and method during data transfers to/from a processing array

Results processing circuits and methods associated with computational memory cells

SONY CORP

Charge shared precharge scheme to reduce compare output delays

High performance dynamic compare circuit

Duty cycle independent tunable clock

Word line voltage supply circuit

System and method for effectively implementing a high speed DRAM device

Digital circuit for performing multicycle addressing in a digital memory

Scheme to test/repair multiple large RAM blocks

HAIG ROBERT

Systems and methods involving multi-bank, dual- or multi-pipe SRAMs

SONY ELECTRONICS INC

Sense amplifier common mode dip filter circuit to avoid false misses