P

Inventor

SAGDEO PIYUSH

US8 patents
⚠️ This page may combine multiple inventors who share the name “SAGDEO PIYUSH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WESTERN DIGITAL TECH INC

4 patents
US10790031B1Sep 29, 2020

System handling for first read read disturb

WESTERN DIGITAL TECH INC4 citations72
US10691372B1Jun 23, 2020

Transistor threshold voltage maintenance in 3D memory

WESTERN DIGITAL TECH INC5 citations70
US11704190B2Jul 18, 2023

UECC failure handling method

WESTERN DIGITAL TECH INC0 citations60
US10936415B2Mar 2, 2021

Error correction scheme in flash memory

WESTERN DIGITAL TECH INC0 citations45

SANDISK TECHNOLOGIES LLC

1 patent
US10235294B1Mar 19, 2019

Pre-read voltage pulse for first read error handling

SANDISK TECHNOLOGIES LLC36 citations93

BHALERAO ABHIJEET

1 patent
US9235470B2Jan 12, 2016

Adaptive EPWR (enhanced post write read) scheduling

BHALERAO ABHIJEET8 citations78

SANDISK TECHNOLOGIES INC

1 patent
US9804922B2Oct 31, 2017

Partial bad block detection and re-use using EPWR for block based architectures

SANDISK TECHNOLOGIES INC5 citations71

KOCHAR MRINAL

1 patent
US9195587B2Nov 24, 2015

Enhanced dynamic read process with single-level cell segmentation

KOCHAR MRINAL3 citations58