Inventor
TALREJA SANJAY S
US19 patents
⚠️ This page may combine multiple inventors who share the name “TALREJA SANJAY S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
18 patentsUS6223290B1Apr 24, 2001
Method and apparatus for preventing the fraudulent use of a cellular telephone
INTEL CORP166 citations98
US5539690AJul 23, 1996
Write verify schemes for flash memory with multilevel cells
INTEL CORP314 citations98
US5485422AJan 16, 1996
Drain bias multiplexing for multiple bit flash cell
INTEL CORP223 citations98
US6154819ANov 28, 2000
Apparatus and method using volatile lock and lock-down registers and for protecting memory blocks
INTEL CORP112 citations96
US5742787AApr 21, 1998
Hardware reset of a write state machine for flash memory
INTEL CORP89 citations96
US6097637AAug 1, 2000
Dynamic single bit per cell to multiple bit per cell memory
INTEL CORP109 citations95
US5944837AAug 31, 1999
Controlling flash memory program and erase pulses
INTEL CORP62 citations95
US5317535AMay 31, 1994
Gate/source disturb protection for sixteen-bit flash EEPROM memory arrays
INTEL CORP132 citations95
US5280447AJan 18, 1994
Floating gate nonvolatile memory with configurable erasure blocks
INTEL CORP105 citations95
US5438546AAug 1, 1995
Programmable redundancy scheme suitable for single-bit state and multibit state nonvolatile memories
INTEL CORP78 citations94
US5907700AMay 25, 1999
Controlling flash memory program and erase pulses
INTEL CORP36 citations92
US6931498B2Aug 16, 2005
Status register architecture for flexible read-while-write device
INTEL CORP28 citations91
US5267196ANov 30, 1993
Floating gate nonvolatile memory with distributed blocking feature
INTEL CORP37 citations91
US6587373B2Jul 1, 2003
Multilevel cell memory architecture
INTEL CORP14 citations84
US6618790B1Sep 9, 2003
Burst suspend and resume with computer memory
INTEL CORP13 citations80
US6483743B1Nov 19, 2002
Multilevel cell memory architecture
INTEL CORP10 citations74
US5379413AJan 3, 1995
User selectable word/byte input architecture for flash EEPROM memory write and erase operations
INTEL CORP13 citations74
US6920539B2Jul 19, 2005
Method and system to retrieve information
INTEL CORP10 citations72