Inventor

SARPATWARI KARTHIK

US80 patents

⚠️ This page may combine multiple inventors who share the name “SARPATWARI KARTHIK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SARPATWARI KARTHIK

MICRON TECHNOLOGY INC

Multi-state programming of memory cells

Identify the programming mode of memory cells during reading of the memory cells

Memory device having 2-transistor vertical memory cell and shared channel region

Multi-step pre-read for write operations in memory devices

Memory device having 2-transistor memory cell and access line plate

Data-based polarity write operations

Restoring memory cell threshold voltages

Identify the programming mode of memory cells based on cell statistics obtained during reading of the memory cells

Read refresh operation

Techniques for applying multiple voltage pulses to select a memory cell

Memory device having 2-transistor memory cell and access line plate

Vertical 2-transistor memory cell

Memory device having 2-transistor vertical memory cell and shield structures

Memory device having 2-transistor memory cell and access line plate

Memory device having 2-transistor vertical memory cell and a common plate

Memory device having 2-transistor vertical memory cell and separate read and write gates

Memory device having 2-transistor vertical memory cell and shield structures

Memory device having 2-transistor vertical memory cell and a common plate

Adaptively programming memory cells in different modes to optimize performance

Memory device having 2-transistor vertical memory cell and shield structures

Memory device having 2-transistor vertical memory cell and wrapped data line structure

Bipolar read retry

Evaluation of background leakage to select write voltage in memory devices

Memory device having shared access line for 2-transistor vertical memory cell

Vertical 3D single word line gain cell with shared read/write bit line

Single word line gain cell with complementary read write channel

Disturb verify for programming memory cells

Accessing a multi-level memory cell

Memory device having shared read/write data line for 2-transistor vertical memory cell

Memory device having 2-transistor vertical memory cell and shared channel region

Memory device having shared access line for 2-transistor vertical memory cell

Memory device having 2-transistor vertical memory cell and shield structures

Memory device having shared read/write access line for 2-transistor vertical memory cell

Inverters, and related memory devices and electronic systems

Single word line gain cell with complementary read write channel

Vertical 3D single word line gain cell with shared read/write bit line

Memory element for weight update in a neural network

Memory device having shared read/write access line for 2-transistor vertical memory cell

Identify the programming mode of memory cells based on cell statistics obtained during reading of the memory cells

Drift aware read operations

Multi-step pre-read for write operations in memory devices

Integrated assemblies comprising hydrogen diffused within two or more different semiconductor materials, and methods of forming integrated assemblies

Identify the programming mode of memory cells during reading of the memory cells

Evaluation of background leakage to select write voltage in memory devices

Memory device having 2-transistor vertical memory cell and wrapped data line structure

Dirty write on power off

Weighted wear leveling for improving uniformity

SARPATWARI KARTHIK

Disturb verify for programming memory cells

Methods for generating random data using phase change materials and related devices and systems

INTEL CORP

Memory structures having improved write endurance