Inventor

GAJERA NEVIL

US17 patents

⚠️ This page may combine multiple inventors who share the name “GAJERA NEVIL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GAJERA NEVIL

MICRON TECHNOLOGY INC

Memory block testing

Restoring memory cell threshold voltages

Iterative decoding technique for correcting DRAM device failures

Modified write voltage for memory devices

Dirty write on power off

Mitigation of voltage threshold drift associated with power down condition of non-volatile memory device

Restoring memory cell threshold voltages

Mitigation of voltage threshold drift associated with power down condition of non-volatile memory device

Instant write scheme with delayed parity/raid

Method and memory system for writing data to dram submodules based on the data traffic demand

Modified write voltage for memory devices

Iterative decoding technique for correcting DRAM device failures

Iterative decoder for correcting dram device failures

Die based trimming

Address mapping for improved memory reliability

Shadow DRAM with CRC+RAID architecture, system and method for high RAS feature in a CXL drive

GATZEMEIER SCOTT N

Memory block testing