Inventor
RYLOV SERGEY V
US22 patents
⚠️ This page may combine multiple inventors who share the name “RYLOV SERGEY V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
12 patentsUS7486145B2Feb 3, 2009
Circuits and methods for implementing sub-integer-N frequency dividers using phase rotators
IBM55 citations94
US6927611B2Aug 9, 2005
Semidigital delay-locked loop using an analog-based finite state machine
IBM38 citations92
US7107301B2Sep 12, 2006
Method and apparatus for reducing latency in a digital signal processing device
IBM11 citations84
US7893861B2Feb 22, 2011
Time-to-digital based analog-to-digital converter architecture
IBM18 citations83
US9698968B2Jul 4, 2017
Phase interpolator calibration
IBM8 citations82
US6903579B2Jun 7, 2005
Pipelined low-voltage current-mode logic with a switching stack height of one
IBM8 citations74
US7659763B2Feb 9, 2010
Conditioning input buffer for clock interpolation
IBM7 citations72
US7602869B2Oct 13, 2009
Methods and apparatus for clock synchronization and data recovery in a receiver
IBM7 citations72
US9306729B2Apr 5, 2016
Phase interpolator calibration
IBM4 citations71
US6859071B2Feb 22, 2005
Pseudofooter circuit for dynamic CMOS (Complementary metal-oxide-semiconductor) logic
IBM3 citations63
US8928384B2Jan 6, 2015
Programmable delay generator and cascaded interpolator
IBM2 citations62
US9253004B2Feb 2, 2016
Apparatus and method for signal phase control in an integrated radio circuit
IBM0 citations52
HYPRES INC
2 patentsBULZACCHELLI JOHN F
2 patentsUS8704583B2Apr 22, 2014
Capacitive level-shifting circuits and methods for adding DC offsets to output of current-integrating amplifier
BULZACCHELLI JOHN F21 citations92
US8774228B2Jul 8, 2014
Timing recovery method and apparatus for an input/output bus with link redundancy
BULZACCHELLI JOHN F1 citations52