Inventor

BENISTANT FRANCIS

SG24 patents

⚠️ This page may combine multiple inventors who share the name “BENISTANT FRANCIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BENISTANT FRANCIS

CHARTERED SEMICONDUCTOR MFG

Method of activating polysilicon gate structure dopants after offset spacer deposition

Semiconductor device layout and channeling implant process

Semiconductor device layout and channeling implant process

Semiconductor device layout and channeling implant process

Shallow low energy ion implantation into pad oxide for improving threshold voltage stability

Structure and method to form source and drain regions over doped depletion regions

GLOBALFOUNDRIES SG PTE LTD

Isolation scheme for high voltage device

System and method for modular simulation of spin transfer torque magnetic random access memory devices

Method for fabricating semiconductor devices with reduced junction diffusion

Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction

Structure and method to form source and drain regions over doped depletion regions

GLOBALFOUNDRIES INC

Multiple-step epitaxial growth S/D regions for NMOS FinFET

FinFET conformal junction and high EPI surface dopant concentration method and device

FinFET conformal junction and high epi surface dopant concentration method and device

FinFET conformal junction and abrupt junction with reduced damage method and device

FinFET conformal junction and abrupt junction with reduced damage method and device

MICRON TECHNOLOGY INC

Modified source/drain re-oxidation method and system

Modified source/drain re-oxidation method and system

Modified source/drain re-oxidation method and system

UNIV SINGAPORE

Method for fabricating semiconductor devices with reduced junction diffusion

BAZIZI EL MEHDI

Semiconductor devices and methods of forming the semiconductor devices including a retrograde well

CHARTERED SEMICONDUCTOR MFG L

Low cost source drain elevation through poly amorphizing implant technology

LI YISUO

Integrated circuit system with double doped drain transistor

POON DEBORA CHYIU HYIA

Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction