P

Inventor

TARROUX GERARD

FR16 patents
⚠️ This page may combine multiple inventors who share the name “TARROUX GERARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CADENCE DESIGN SYSTEMS INC

14 patents
US6397370B1May 28, 2002

Method and system for breaking complex Boolean networks

CADENCE DESIGN SYSTEMS INC19 citations91
US9092586B1Jul 28, 2015

Version management mechanism for fluid guard ring PCells

CADENCE DESIGN SYSTEMS INC28 citations90
US8347261B2Jan 1, 2013

Method and system for implementing graphically editable parameterized cells

CADENCE DESIGN SYSTEMS INC16 citations88
US7555739B1Jun 30, 2009

Method and apparatus for maintaining synchronization between layout clones

CADENCE DESIGN SYSTEMS INC41 citations86
US9842183B1Dec 12, 2017

Methods and systems for enabling concurrent editing of electronic circuit layouts

CADENCE DESIGN SYSTEMS INC12 citations81
US9761204B1Sep 12, 2017

System and method for accelerated graphic rendering of design layout having variously sized geometric objects

CADENCE DESIGN SYSTEMS INC11 citations80
US9208273B1Dec 8, 2015

Methods, systems, and articles of manufacture for implementing clone design components in an electronic design

CADENCE DESIGN SYSTEMS INC11 citations79
US8527934B2Sep 3, 2013

Method and system for implementing graphically editable parameterized cells

CADENCE DESIGN SYSTEMS INC15 citations79
US10783312B1Sep 22, 2020

Methods, systems, and computer program product for determining layout equivalence for a multi-fabric electronic design

CADENCE DESIGN SYSTEMS INC4 citations71
US10922469B1Feb 16, 2021

Methods and systems of enabling concurrent editing of hierarchical electronic circuit layouts

CADENCE DESIGN SYSTEMS INC4 citations70
US10671793B1Jun 2, 2020

Editing of layout designs for fixing DRC violations

CADENCE DESIGN SYSTEMS INC5 citations70
US9773082B1Sep 26, 2017

Circuit design employing stamp patterns

CADENCE DESIGN SYSTEMS INC4 citations68
US9684748B1Jun 20, 2017

System and method for identifying an electrical short in an electronic design

CADENCE DESIGN SYSTEMS INC4 citations64
US9542084B1Jan 10, 2017

System and method for generating vias in an electronic design by automatically using a hovering cursor indication

CADENCE DESIGN SYSTEMS INC5 citations63

VLSI TECHNOLOGY INC

2 patents