Inventor
SHETH DHVANI
US6 patents
Patents
6 patentsUS11250895B1Feb 15, 2022
Systems and methods for driving wordlines using set-reset latches
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US11568904B1Jan 31, 2023
Memory with positively boosted write multiplexer
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US12451171B2Oct 21, 2025
High-speed and area-efficient parallel-write-and-read memory
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US12094528B2Sep 17, 2024
Memory with double redundancy
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US12125526B2Oct 22, 2024
Memory with bitcell power boosting
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US11894050B2Feb 6, 2024
Memory with a sense amplifier isolation scheme for enhancing memory read bandwidth
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