Inventor
CHIN CHIH-YUN
TW12 patents
Patents
12 patentsUS10483396B1Nov 19, 2019
Interfacial layer between fin and source/drain region
TAIWAN SEMICONDUCTOR MFG CO LTD10 citations83
US12191393B2Jan 7, 2025
Low Ge isolated epitaxial layer growth over nano-sheet architecture design for RP reduction
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations64
US11855142B2Dec 26, 2023
Supportive layer in source/drains of FinFET devices
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11476331B2Oct 18, 2022
Supportive layer in source/drains of FinFET devices
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US12336210B2Jun 17, 2025
Source/drain structure for semiconductor device
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations61
US11735668B2Aug 22, 2023
Interfacial layer between fin and source/drain region
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations61
US11575026B2Feb 7, 2023
Source/drain structure for semiconductor device
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations61
US11482620B2Oct 25, 2022
Interfacial layer between Fin and source/drain region
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations61
US10944005B2Mar 9, 2021
Interfacial layer between fin and source/drain region
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations61
US11264237B2Mar 1, 2022
Method of epitaxy and semiconductor device
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations51
US10854715B2Dec 1, 2020
Supportive layer in source/drains of FinFET devices
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations51
US10164097B2Dec 25, 2018
Semiconductor device and manufacturing method thereof
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations51