Inventor
CHEN TUNG-PO
TW29 patents
⚠️ This page may combine multiple inventors who share the name “CHEN TUNG-PO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
UNITED MICROELECTRONICS CORP
26 patentsUS6228730B1May 8, 2001
Method of fabricating field effect transistor
UNITED MICROELECTRONICS CORP89 citations98
US6255152B1Jul 3, 2001
Method of fabricating CMOS using Si-B layer to form source/drain extension junction
UNITED MICROELECTRONICS CORP65 citations96
US6177334B1Jan 23, 2001
Manufacturing method capable of preventing corrosion of metal oxide semiconductor
UNITED MICROELECTRONICS CORP23 citations92
US6133130AOct 17, 2000
Method for fabricating an embedded dynamic random access memory using self-aligned silicide technology
UNITED MICROELECTRONICS CORP35 citations92
US6022795AFeb 8, 2000
Salicide formation process
UNITED MICROELECTRONICS CORP23 citations92
US6316321B1Nov 13, 2001
Method for forming MOSFET
UNITED MICROELECTRONICS CORP18 citations84
US6225155B1May 1, 2001
Method of forming salicide in embedded dynamic random access memory
UNITED MICROELECTRONICS CORP15 citations84
US6297112B1Oct 2, 2001
Method of forming a MOS transistor
UNITED MICROELECTRONICS CORP14 citations74
US6187644B1Feb 13, 2001
Method of removing oxynitride by forming an offset spacer
UNITED MICROELECTRONICS CORP8 citations74
US6156633ADec 5, 2000
Process for forming high temperature stable self-aligned metal silicide layer
UNITED MICROELECTRONICS CORP9 citations74
US6156126ADec 5, 2000
Method for reducing or avoiding the formation of a silicon recess in SDE junction regions
UNITED MICROELECTRONICS CORP8 citations74
US6150205ANov 21, 2000
Method of fabricating dual gate
UNITED MICROELECTRONICS CORP7 citations74
US6124621ASep 26, 2000
Structure of a spacer
UNITED MICROELECTRONICS CORP11 citations74
US5970379AOct 19, 1999
Method of reducing loss of metal silicide in pre-metal etching
UNITED MICROELECTRONICS CORP9 citations74
US5858849AJan 12, 1999
Method of manufacturing self-aligned silicide
UNITED MICROELECTRONICS CORP13 citations74
US6187674B1Feb 13, 2001
Manufacturing method capable of preventing corrosion and contamination of MOS gate
UNITED MICROELECTRONICS CORP9 citations73
US5893751AApr 13, 1999
Self-aligned silicide manufacturing method
UNITED MICROELECTRONICS CORP14 citations73
US6060349AMay 9, 2000
Planarization on an embedded dynamic random access memory
UNITED MICROELECTRONICS CORP13 citations71
US6670249B1Dec 30, 2003
Process for forming high temperature stable self-aligned metal silicide layer
UNITED MICROELECTRONICS CORP3 citations63
US6426256B1Jul 30, 2002
Method for fabricating an embedded DRAM with self-aligned borderless contacts
UNITED MICROELECTRONICS CORP5 citations63
US6350646B1Feb 26, 2002
Method for reducing thermal budget in node contact application
UNITED MICROELECTRONICS CORP2 citations63
US6197672B1Mar 6, 2001
Method for forming polycide dual gate
UNITED MICROELECTRONICS CORP6 citations63
US6153520ANov 28, 2000
Method for fabricating self-aligned silicide
UNITED MICROELECTRONICS CORP6 citations63
US6316311B1Nov 13, 2001
Method of forming borderless contact
UNITED MICROELECTRONICS CORP4 citations62
US6010958AJan 4, 2000
Method for improving the planarization of dielectric layer in the fabrication of metallic interconnects
UNITED MICROELECTRONICS CORP6 citations62
US6277721B1Aug 21, 2001
Salicide formation process
UNITED MICROELECTRONICS CORP1 citations52