Inventor
CABOT MASON B
US12 patents
⚠️ This page may combine multiple inventors who share the name “CABOT MASON B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
10 patentsUS7200713B2Apr 3, 2007
Method of implementing off-chip cache memory in dual-use SRAM memory for network processors
INTEL CORP61 citations97
US7577792B2Aug 18, 2009
Heterogeneous processors sharing a common cache
INTEL CORP20 citations92
US7360031B2Apr 15, 2008
Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces
INTEL CORP30 citations92
US8799579B2Aug 5, 2014
Caching for heterogeneous processors
INTEL CORP5 citations84
US7302528B2Nov 27, 2007
Caching bypass
INTEL CORP10 citations83
US6687821B1Feb 3, 2004
System for dynamically configuring system logic device coupled to the microprocessor to optimize application performance by reading from selection table located in non-volatile memory
INTEL CORP14 citations83
US9235550B2Jan 12, 2016
Caching for heterogeneous processors
INTEL CORP1 citations63
US7401184B2Jul 15, 2008
Matching memory transactions to cache line boundaries
INTEL CORP4 citations62
US7266626B2Sep 4, 2007
Method and apparatus for connecting an additional processor to a bus with symmetric arbitration
INTEL CORP0 citations49
US6437783B1Aug 20, 2002
Method and system for simultaneously displaying the throughput on multiple busses
INTEL CORP1 citations45