Inventor
LIN YIH-SHUNG
SG40 patents
⚠️ This page may combine multiple inventors who share the name “LIN YIH-SHUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SGS THOMSON MICROELECTRONICS
14 patentsUS5435888AJul 25, 1995
Enhanced planarization technique for an integrated circuit
SGS THOMSON MICROELECTRONICS88 citations97
US5658828AAug 19, 1997
Method for forming an aluminum contact through an insulating layer
SGS THOMSON MICROELECTRONICS49 citations96
US5108951AApr 28, 1992
Method for forming a metal contact
SGS THOMSON MICROELECTRONICS80 citations96
US5652464AJul 29, 1997
Integrated circuit with a titanium nitride contact barrier having oxygen stuffed grain boundaries
SGS THOMSON MICROELECTRONICS43 citations94
US5514908AMay 7, 1996
Integrated circuit with a titanium nitride contact barrier having oxygen stuffed grain boundaries
SGS THOMSON MICROELECTRONICS88 citations93
US5485035AJan 16, 1996
Method for planarization of an integrated circuit
SGS THOMSON MICROELECTRONICS23 citations91
US5246883ASep 21, 1993
Semiconductor contact via structure and method
SGS THOMSON MICROELECTRONICS22 citations91
US4978637ADec 18, 1990
Local interconnect process for integrated circuits
SGS THOMSON MICROELECTRONICS20 citations82
US5597983AJan 28, 1997
Process of removing polymers in semiconductor vias
SGS THOMSON MICROELECTRONICS14 citations74
US5412868AMay 9, 1995
Process of removing polymers in semiconductor vias
SGS THOMSON MICROELECTRONICS8 citations74
US4933304AJun 12, 1990
Method for reducing the surface reflectance of a metal layer during semiconductor processing
SGS THOMSON MICROELECTRONICS18 citations74
US5633534AMay 27, 1997
Integrated circuit with enhanced planarization
SGS THOMSON MICROELECTRONICS1 citations63
USRE35111EDec 5, 1995
Local interconnect process for integrated circuits
SGS THOMSON MICROELECTRONICS4 citations63
US5075761ADec 24, 1991
Local interconnect for integrated circuits
SGS THOMSON MICROELECTRONICS2 citations63
ST MICROELECTRONICS INC
12 patentsUS5841195ANov 24, 1998
Semiconductor contact via structure
ST MICROELECTRONICS INC45 citations94
US5943598AAug 24, 1999
Integrated circuit with planarized dielectric layer between successive polysilicon layers
ST MICROELECTRONICS INC23 citations92
US5837613ANov 17, 1998
Enhanced planarization technique for an integrated circuit
ST MICROELECTRONICS INC19 citations92
US6191033B1Feb 20, 2001
Method of fabricating an integrated circuit with improved contact barrier
ST MICROELECTRONICS INC15 citations91
US5986330ANov 16, 1999
Enhanced planarization technique for an integrated circuit
ST MICROELECTRONICS INC13 citations82
USRE39690EJun 12, 2007
Enhanced planarization technique for an integrated circuit
ST MICROELECTRONICS INC9 citations74
US5976969ANov 2, 1999
Method for forming an aluminum contact
ST MICROELECTRONICS INC11 citations74
US6433435B2Aug 13, 2002
Aluminum contact structure for integrated circuits
ST MICROELECTRONICS INC3 citations63
US5930673AJul 27, 1999
Method for forming a metal contact
ST MICROELECTRONICS INC4 citations63
US6617242B1Sep 9, 2003
Method for fabricating interlevel contacts of aluminum/refractory metal alloys
ST MICROELECTRONICS INC6 citations62
US6242811B1Jun 5, 2001
Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperature
ST MICROELECTRONICS INC5 citations62
US6291344B1Sep 18, 2001
Integrated circuit with improved contact barrier
ST MICROELECTRONICS INC3 citations59
TAIWAN SEMICONDUCTOR MFG
8 patentsUS7176137B2Feb 13, 2007
Method for multiple spacer width control
TAIWAN SEMICONDUCTOR MFG101 citations98
US6943077B2Sep 13, 2005
Selective spacer layer deposition method for forming spacers with different widths
TAIWAN SEMICONDUCTOR MFG24 citations92
US7118451B2Oct 10, 2006
CMP apparatus and process sequence method
TAIWAN SEMICONDUCTOR MFG20 citations89
US6746900B1Jun 8, 2004
Method for forming a semiconductor device having high-K gate dielectric material
TAIWAN SEMICONDUCTOR MFG17 citations84
US7004814B2Feb 28, 2006
CMP process control method
TAIWAN SEMICONDUCTOR MFG11 citations82
US7271103B2Sep 18, 2007
Surface treated low-k dielectric as diffusion barrier for copper metallization
TAIWAN SEMICONDUCTOR MFG8 citations74
US7294043B2Nov 13, 2007
CMP apparatus and process sequence method
TAIWAN SEMICONDUCTOR MFG4 citations59
US7011929B2Mar 14, 2006
Method for forming multiple spacer widths
TAIWAN SEMICONDUCTOR MFG0 citations42
CHARTERED SEMICONDUCTOR MFG
6 patentsUS6207554B1Mar 27, 2001
Gap filling process in integrated circuits using low dielectric constant materials
CHARTERED SEMICONDUCTOR MFG39 citations90
US6183189B1Feb 6, 2001
Self aligning wafer chuck design for wafer processing tools
CHARTERED SEMICONDUCTOR MFG35 citations89
US6127238AOct 3, 2000
Plasma enhanced chemical vapor deposited (PECVD) silicon nitride barrier layer for high density plasma chemical vapor deposited (HDP-CVD) dielectric layer
CHARTERED SEMICONDUCTOR MFG21 citations89
US6558739B1May 6, 2003
Titanium nitride/titanium tungsten alloy composite barrier layer for integrated circuits
CHARTERED SEMICONDUCTOR MFG11 citations73
US6054390AApr 25, 2000
Grazing incident angle processing method for microelectronics layer fabrication
CHARTERED SEMICONDUCTOR MFG9 citations73
US5918152AJun 29, 1999
Gap filling method using high pressure
CHARTERED SEMICONDUCTOR MFG13 citations71