Inventor

WICKERAAD JOHN A

US35 patents

⚠️ This page may combine multiple inventors who share the name “WICKERAAD JOHN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WICKERAAD JOHN A

HEWLETT PACKARD DEVELOPMENT CO

Apparatus and method for ensuring forward progress in coherent I/O systems

Packet protection for header modification

System and method for multiple cycle capture of chip state

Systems and methods for prefetch operations to reduce latency associated with memory access

System and method for multiple cycle capture of chip state

Using read current transactions for improved performance in directory-based coherent I/O systems

Apparatus and method for tracking flushes of cache entries in a data processing system

Per cache line semaphore for cache access arbitration

Apparatus and method to align clocks for repeatable system testing

Performance adder for tracking occurrence of events within a circuit

Method and apparatus to determine when all outstanding fetches are complete

TCAM BIST with redundancy

Content addressable memory

Content addressable memory

Performance adder for tracking occurrence of events within a circuit

Method and apparatus for generating timeouts to a system based counting intervals supplied by a shared counting device

Signals crossing multiple clock domains

TCAM BIST with redundancy

Encapsulating packets for network chip conduit port

Application specific integrated circuit with internal testing

Apparatus and method for completing transactions in all flow control classes

Content addressable memory address resolver

Conduit port for network chips

HEWLETT PACKARD ENTPR DEV LP

Dynamic allocation of resources within network devices

Generating a hash table in accordance with a prefix length

Dynamic allocation of hash table resources

Content addressable memory

Combining prefix lengths into a hash table

Content addressable memory

HEWLETT PACKARD CO

Method and apparatus for replacing cache lines in a cache memory

Single channel encoder system

Method and apparatus for using the unused bits of a data packet to transmit additional information

Delaying clock and data signals to force synchronous operation in digital systems that determine phase relationships between clocks with related frequencies

HEWLETT PACKARD ENETRPRISE DEV LP

Data tables in content addressable memory

LAVIGNE BRUCE E

Support chip for handling network chips on a network device