Inventor
KARCHMER DAVID
US27 patents
⚠️ This page may combine multiple inventors who share the name “KARCHMER DAVID”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
21 patentsUS6026226AFeb 15, 2000
Local compilation in context within a design hierarchy
ALTERA CORP157 citations97
US6167364ADec 26, 2000
Methods and apparatus for automatically generating interconnect patterns in programmable logic devices
ALTERA CORP58 citations94
US7853911B1Dec 14, 2010
Method and apparatus for performing path-level skew optimization and analysis for a logic design
ALTERA CORP15 citations92
US7669157B1Feb 23, 2010
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches
ALTERA CORP28 citations92
US7275232B2Sep 25, 2007
Methods for producing equivalent field-programmable gate arrays and structured application specific integrated circuits
ALTERA CORP24 citations92
US7784008B1Aug 24, 2010
Performance visualization system
ALTERA CORP20 citations90
US6697773B1Feb 24, 2004
Using assignment decision diagrams with control nodes for sequential review during behavioral simulation
ALTERA CORP20 citations90
US7464362B1Dec 9, 2008
Method and apparatus for performing incremental compilation
ALTERA CORP12 citations83
US7231337B1Jun 12, 2007
Using assignment decision diagrams with control nodes for sequential review during behavioral simulation
ALTERA CORP10 citations82
US6173245B1Jan 9, 2001
Programmable logic array device design using parameterized logic modules
ALTERA CORP17 citations82
US7584443B1Sep 1, 2009
Clock domain conflict analysis for timing graphs
ALTERA CORP19 citations81
US7577929B1Aug 18, 2009
Early timing estimation of timing statistical properties of placement
ALTERA CORP6 citations74
US6961690B1Nov 1, 2005
Behaviorial digital simulation using hybrid control and data flow representations
ALTERA CORP8 citations71
US7064580B2Jun 20, 2006
Mask-programmable logic device with programmable portions
ALTERA CORP5 citations69
US7587688B1Sep 8, 2009
User-directed timing-driven synthesis
ALTERA CORP4 citations63
US5768562AJun 16, 1998
Methods for implementing logic in auxiliary components associated with programmable logic array devices
ALTERA CORP6 citations63
US7877721B2Jan 25, 2011
Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits
ALTERA CORP4 citations62
US8001537B1Aug 16, 2011
Method and apparatus for compiling programmable logic device configurations
ALTERA CORP3 citations61
US7725856B1May 25, 2010
Method and apparatus for performing parallel slack computation
ALTERA CORP4 citations61
US7358766B2Apr 15, 2008
Mask-programmable logic device with programmable portions
ALTERA CORP4 citations58
US9122826B1Sep 1, 2015
Method and apparatus for performing compilation using multiple design flows
ALTERA CORP0 citations52