Inventor

DRERUP BERNARD CHARLES

US39 patents

⚠️ This page may combine multiple inventors who share the name “DRERUP BERNARD CHARLES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DRERUP BERNARD CHARLES

IBM

System and method for controlling data transfer between multiple interconnected computer systems with a portable input device

Method and system for executing a non-native stack-based instruction within a computer system

Method and system for translating a non-native bytecode to a set of codes native to a processor within a computer system

Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanism

Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanism

Reducing power in a snooping cache based multiprocessor environment

Method and system for executing a non-native mode-sensitive instruction within a computer system

Low latency cadence selectable interface for data transfers between busses of differing frequencies

Utilizing programmable channels for allocation of buffer space and transaction control in data communications

Directory for multi-node coherent bus

Data communication method and apparatus utilizing programmable channels for allocation of buffer space and transaction control

Internal data bus interconnection mechanism utilizing central interconnection module converting data in different alignment domains

Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target

System on a chip bus with automatic pipeline stage insertion for timing closure

Ensuring orderly forward progress in granting snoop castout requests

Cache intervention on a separate data bus when on-chip bus has separate read and write data busses

Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanism

System and method for providing improved bus utilization via target directed completion

Method for moving snoop pushes to the front of a request queue

Method and apparatus for attaching multiple slave devices to a single bus controller interface while supporting command pipelining

Method, apparatus, and computer program product for optimizing packet flow control through buffer status forwarding

Method and bus prefetching mechanism for implementing enhanced buffer control

Multiprocessor environment supporting variable-sized coherency transactions

Method, apparatus and computer program product for write data transfer

Dynamic cache coherency snooper presence with variable snoop latency

Method and apparatus for passing messages through a bus-to-bus bridge while maintaining ordering

Data path master/slave data processing device apparatus and method

Method and apparatus for periodic phase alignment

Dynamic phase alignment circuit

Directory for multi-node coherent bus

Method and bus prefetching mechanism for implementing enhanced buffer control

System on a chip bus with automatic pipeline stage insertion for timing closure

Voltage indicator signal generation system and method

Data path master/slave data processing device apparatus

DRERUP BERNARD CHARLES

Structure for maintaining memory data integrity in a processor integrated circuit using cache coherency protocols

Method and apparatus for maintaining memory data integrity in an information handling system using cache coherency protocols

BIRMIWAL PARAG

Voltage indicator signal generation system and method

Voltage indicator signal generation system and method

ARIMILLI LAKSHMINARAYANA BABA

Processor system and methods of triggering a block move using a system bus write command initiated by user code