Inventor

WOLFORD BARRY JOE

US31 patents

⚠️ This page may combine multiple inventors who share the name “WOLFORD BARRY JOE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WOLFORD BARRY JOE

IBM

Configurable DDR write-channel phase advance and delay capability

Memory clock generation with configurable phase advance and delay capability

Reducing power in a snooping cache based multiprocessor environment

N-way psuedo cross-bar having an arbitration feature using discrete processor local busses

Method and apparatus for sampling double data rate memory read data

Method and apparatus for supporting N-bit width DDR memory interface using a common symmetrical read data path with 2N-bit internal bus width

Generation of a synthetic clock signal in synchronism with a high frequency clock signal and corresponding to a low frequency clock signal

Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target

System on a chip bus with automatic pipeline stage insertion for timing closure

Ensuring orderly forward progress in granting snoop castout requests

System and method for providing improved bus utilization via target directed completion

Method for moving snoop pushes to the front of a request queue

Method and bus prefetching mechanism for implementing enhanced buffer control

Multiprocessor environment supporting variable-sized coherency transactions

Method, apparatus and computer program product for write data transfer

Dynamic cache coherency snooper presence with variable snoop latency

Data path master/slave data processing device apparatus and method

Method and apparatus to reduce system bus latency on a cache miss with address acknowledgments

Method and bus prefetching mechanism for implementing enhanced buffer control

System on a chip bus with automatic pipeline stage insertion for timing closure

Data path master/slave data processing device apparatus

Tri-state bus contention circuit preventing false switching caused by poor synchronization

Method, apparatus, and computer program product for pacing clocked operations

QUALCOMM INC

System and method to reduce dynamic RAM power consumption via the use of valid data indicators

Device directed memory barriers

Method and apparatus for obtaining memory status information cross-reference to related applications

Concurrent status register read

Method and apparatus for conditional broadcast of barrier operations

HOFMANN RICHARD GERARD

Method of associating groups of classified source addresses with vibration patterns

WOLFORD BARRY JOE

Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem

GANASAN JAYA PRAKASH SUBRAMANIAM

Method and apparatus for scalable network transaction identifier for interconnects