Inventor

YU BIN

CN640 patents

⚠️ This page may combine multiple inventors who share the name “YU BIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YU BIN

ADVANCED MICRO DEVICES INC

Narrow fin FinFET

Strained channel FinFET

Method for forming multiple fins in a semiconductor device

Epitaxially grown fin for FinFET

Semiconductor device having a U-shaped gate structure

Strained channel finfet

Fully depleted SOI transistor with elevated source and drain

Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation

Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device

FinFET device with multiple fin structures

Double spacer FinFET formation

Method for forming multiple structures in a semiconductor device

Semiconductor-on-insulator circuit with multiple work functions

Damascene gate process with sacrificial oxide in semiconductor devices

Formation of well-controlled thin SiO, SiN, SiON layer for multilayer high-K dielectric applications

Transistor with local insulator structure

Shallow trench isolation (STI) region with high-K liner and method of formation

MOSFET having a double gate

Method for forming fins in a FinFET device using sacrificial carbon layer

Double gate semiconductor device having separate gates

Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology

Low temperature process for a thin film transistor

Mos transistor with dual metal gate structure

MOS transistor with reduced floating body effect

MOSFETs with differing gate dielectrics and method of formation

MOSFET device having high-K dielectric layer

Method of forming a double gate transistor having an epitaxial silicon/germanium channel region

Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology

Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed

Multiple active layer structure and a method of making such a structure

Process for forming gate conductors

Process for forming multiple active lines and gate-all-around MOSFET

Method of manufacturing a transistor with local insulator structure

MOS transistor with assisted-gates and ultra-shallow “Psuedo” source and drain extensions for ultra-large-scale integration

Method of fabricating an integrated circuit having punch-through suppression

MOS transistor with dual metal gate structure

Reversed T-shaped FinFET

Method for forming a tri-gate MOSFET

Multi-step chemical mechanical polishing of a gate area in a FinFET

Method for forming tri-gate FinFET with mesa isolation

Method for forming a fin in a finFET device

Systems and methods for forming dense n-channel and p-channel fins using shadow implanting

Double-gate vertical MOSFET transistor and fabrication method

Narrow fin FinFET

Uniformly doped source/drain junction in a double-gate MOSFET

Method for forming channels in a finfet device

Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semiconductor substrate

Dual laser anneal for graded halo profile

SOI device with metal source/drain and method of fabrication

ADVANCE MICRO DEVICES INC

Asymmetrical double gate or all-around gate MOSFET devices and methods for making same